Simulation Results: csrng

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.42 %
  • code
  • 92.31 %
  • assert
  • 94.32 %
  • func
  • 75.62 %
  • block
  • 96.95 %
  • line
  • 97.73 %
  • branch
  • 92.43 %
  • toggle
  • 93.37 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
91.67%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 98.295us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 16.454us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 15.358us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 15.000s 1173.989us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 82.281us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 84.190us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 15.358us 1 1 100.00
csrng_csr_aliasing 4.000s 82.281us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
alerts 1 1 100.00
csrng_alert 7.000s 144.651us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
cmds 0 1 0.00
csrng_cmds 5.000s 381.630us 0 1 0.00
life cycle 0 1 0.00
csrng_cmds 5.000s 381.630us 0 1 0.00
stress_all 1 1 100.00
csrng_stress_all 171.000s 6152.616us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 17.889us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 28.724us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 6.000s 212.709us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 6.000s 212.709us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 16.454us 1 1 100.00
csrng_csr_rw 2.000s 15.358us 1 1 100.00
csrng_csr_aliasing 4.000s 82.281us 1 1 100.00
csrng_same_csr_outstanding 2.000s 27.973us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 16.454us 1 1 100.00
csrng_csr_rw 2.000s 15.358us 1 1 100.00
csrng_csr_aliasing 4.000s 82.281us 1 1 100.00
csrng_same_csr_outstanding 2.000s 27.973us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 2.000s 70.644us 1 1 100.00
csrng_tl_intg_err 7.000s 821.163us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_regwen 2.000s 24.234us 1 1 100.00
csrng_csr_rw 2.000s 15.358us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 7.000s 144.651us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 171.000s 6152.616us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
csrng_sec_cm 2.000s 70.644us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
csrng_sec_cm 2.000s 70.644us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
csrng_sec_cm 2.000s 70.644us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
csrng_sec_cm 2.000s 70.644us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
csrng_sec_cm 2.000s 70.644us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 7.000s 144.651us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 171.000s 6152.616us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 7.000s 144.651us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 7.000s 821.163us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
csrng_sec_cm 2.000s 70.644us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
csrng_sec_cm 2.000s 70.644us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 260.182us 1 1 100.00
csrng_err 2.000s 20.078us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 2.000s 88.398us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_scoreboard.sv:671) [scoreboard] Check failed cs_item[app].genbits_q[i] == prd_genbits_q[app][i] (* [*] vs * [*]) 1 test run
csrng_cmds 35497184361316856616446777904136950194601065868788092354406674663424364745448 100
UVM_INFO @ 381630162 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL sequencer [SEQ_NOT_DONE] Sequence m_edn_push_seq[*] already started 1 test run
csrng_stress_all_with_rand_reset 58100618668899568514031356233018420533012149705896814858864341401851829215708 110
UVM_INFO @ 88397898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---