Simulation Results: edn/edn0

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.55 %
  • code
  • 86.10 %
  • assert
  • 96.96 %
  • func
  • 76.59 %
  • line
  • 98.32 %
  • branch
  • 94.28 %
  • cond
  • 86.48 %
  • toggle
  • 92.29 %
  • FSM
  • 59.14 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 30.606us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.880s 19.848us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.770s 25.634us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.940s 965.141us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.390s 42.187us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.820s 141.623us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.770s 25.634us 1 1 100.00
edn_csr_aliasing 1.390s 42.187us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.600s 66.907us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.600s 66.907us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.600s 66.907us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.850s 29.312us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.280s 60.281us 1 1 100.00
errs 1 1 100.00
edn_err 0.930s 31.226us 1 1 100.00
disable 2 2 100.00
edn_disable 0.800s 13.848us 1 1 100.00
edn_disable_auto_req_mode 1.110s 225.897us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.100s 487.389us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.850s 17.379us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.080s 36.173us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.150s 167.699us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.150s 167.699us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.880s 19.848us 1 1 100.00
edn_csr_rw 0.770s 25.634us 1 1 100.00
edn_csr_aliasing 1.390s 42.187us 1 1 100.00
edn_same_csr_outstanding 1.180s 138.865us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.880s 19.848us 1 1 100.00
edn_csr_rw 0.770s 25.634us 1 1 100.00
edn_csr_aliasing 1.390s 42.187us 1 1 100.00
edn_same_csr_outstanding 1.180s 138.865us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.260s 1050.340us 1 1 100.00
edn_tl_intg_err 1.430s 98.530us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.850s 30.423us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.280s 60.281us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.260s 1050.340us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.260s 1050.340us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.260s 1050.340us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.260s 1050.340us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.280s 60.281us 1 1 100.00
edn_sec_cm 3.260s 1050.340us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.280s 60.281us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.430s 98.530us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 14.210s 945.200us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 46823909959040965448173640633603615738977350665095156625697832274739352741521 177
UVM_INFO @ 945199865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---