Simulation Results: edn/edn1

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.82 %
  • code
  • 82.41 %
  • assert
  • 98.44 %
  • func
  • 79.62 %
  • line
  • 98.10 %
  • branch
  • 92.64 %
  • cond
  • 87.38 %
  • toggle
  • 94.16 %
  • FSM
  • 39.77 %
Validation stages
V1
100.00%
V2
92.86%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.750s 51.558us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.820s 17.109us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.760s 45.962us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.660s 276.899us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.250s 150.190us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.920s 46.617us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.760s 45.962us 1 1 100.00
edn_csr_aliasing 1.250s 150.190us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.950s 79.049us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.950s 79.049us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.950s 79.049us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.810s 22.272us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.030s 29.537us 1 1 100.00
errs 1 1 100.00
edn_err 0.850s 68.116us 1 1 100.00
disable 1 2 50.00
edn_disable 0.720s 14.260us 1 1 100.00
edn_disable_auto_req_mode 0.710s 14.875us 0 1 0.00
stress_all 1 1 100.00
edn_stress_all 2.410s 896.577us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.790s 14.941us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.870s 21.853us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.110s 170.380us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.110s 170.380us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.820s 17.109us 1 1 100.00
edn_csr_rw 0.760s 45.962us 1 1 100.00
edn_csr_aliasing 1.250s 150.190us 1 1 100.00
edn_same_csr_outstanding 0.820s 28.729us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.820s 17.109us 1 1 100.00
edn_csr_rw 0.760s 45.962us 1 1 100.00
edn_csr_aliasing 1.250s 150.190us 1 1 100.00
edn_same_csr_outstanding 0.820s 28.729us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 2.340s 652.386us 1 1 100.00
edn_tl_intg_err 1.920s 907.882us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.840s 53.140us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.030s 29.537us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.340s 652.386us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 2.340s 652.386us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 2.340s 652.386us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 2.340s 652.386us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.030s 29.537us 1 1 100.00
edn_sec_cm 2.340s 652.386us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.030s 29.537us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.920s 907.882us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 17.140s 3948.481us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (edn_scoreboard.sv:428) [scoreboard] Check failed (cs_cmd == sw_cmd_req_comp) Additional data * in auto_req_mode has to match the value from sw_cmd_req register *xxxxxxxxx. 1 test run
edn_disable_auto_req_mode 72099315757043652133007015659583617713824087883693290602130962590719985429720 88
UVM_INFO @ 14874880 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---