Simulation Results: entropy_src/rng_4bits

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 72.51 %
  • code
  • 85.12 %
  • assert
  • 84.56 %
  • func
  • 47.85 %
  • block
  • 93.89 %
  • line
  • 96.59 %
  • branch
  • 85.43 %
  • toggle
  • 76.18 %
  • FSM
  • 82.29 %
Validation stages
V1
83.33%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
entropy_src_smoke 2.000s 39.192us 1 1 100.00
csr_hw_reset 1 1 100.00
entropy_src_csr_hw_reset 2.000s 92.400us 1 1 100.00
csr_rw 1 1 100.00
entropy_src_csr_rw 2.000s 115.711us 1 1 100.00
csr_bit_bash 1 1 100.00
entropy_src_csr_bit_bash 7.000s 485.640us 1 1 100.00
csr_aliasing 1 1 100.00
entropy_src_csr_aliasing 3.000s 65.675us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
entropy_src_csr_mem_rw_with_rand_reset 1.000s 5.905us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
entropy_src_csr_rw 2.000s 115.711us 1 1 100.00
entropy_src_csr_aliasing 3.000s 65.675us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 3 3 100.00
entropy_src_smoke 2.000s 39.192us 1 1 100.00
entropy_src_rng 57.000s 13086.904us 1 1 100.00
entropy_src_fw_ov 64.000s 14198.247us 1 1 100.00
firmware_mode 1 1 100.00
entropy_src_fw_ov 64.000s 14198.247us 1 1 100.00
rng_mode 1 1 100.00
entropy_src_rng 57.000s 13086.904us 1 1 100.00
rng_max_rate 1 1 100.00
entropy_src_rng_max_rate 207.000s 14039.623us 1 1 100.00
health_checks 1 1 100.00
entropy_src_rng 57.000s 13086.904us 1 1 100.00
conditioning 1 1 100.00
entropy_src_rng 57.000s 13086.904us 1 1 100.00
interrupts 2 2 100.00
entropy_src_rng 57.000s 13086.904us 1 1 100.00
entropy_src_intr 2.000s 229.865us 1 1 100.00
alerts 2 2 100.00
entropy_src_rng 57.000s 13086.904us 1 1 100.00
entropy_src_functional_alerts 3.000s 667.202us 1 1 100.00
stress_all 1 1 100.00
entropy_src_stress_all 198.000s 14067.148us 1 1 100.00
functional_errors 1 1 100.00
entropy_src_functional_errors 1.000s 118.503us 1 1 100.00
firmware_ov_read_contiguous_data 1 1 100.00
entropy_src_fw_ov_contiguous 2.000s 43.685us 1 1 100.00
intr_test 1 1 100.00
entropy_src_intr_test 1.000s 62.536us 1 1 100.00
alert_test 1 1 100.00
entropy_src_alert_test 2.000s 44.042us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
entropy_src_tl_errors 3.000s 153.014us 1 1 100.00
tl_d_illegal_access 1 1 100.00
entropy_src_tl_errors 3.000s 153.014us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 92.400us 1 1 100.00
entropy_src_csr_rw 2.000s 115.711us 1 1 100.00
entropy_src_csr_aliasing 3.000s 65.675us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 72.628us 1 1 100.00
tl_d_partial_access 4 4 100.00
entropy_src_csr_hw_reset 2.000s 92.400us 1 1 100.00
entropy_src_csr_rw 2.000s 115.711us 1 1 100.00
entropy_src_csr_aliasing 3.000s 65.675us 1 1 100.00
entropy_src_same_csr_outstanding 2.000s 72.628us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
entropy_src_sec_cm 2.000s 278.497us 1 1 100.00
entropy_src_tl_intg_err 3.000s 124.260us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
entropy_src_rng 57.000s 13086.904us 1 1 100.00
entropy_src_cfg_regwen 2.000s 71.080us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
entropy_src_rng 57.000s 13086.904us 1 1 100.00
sec_cm_config_redun 1 1 100.00
entropy_src_rng 57.000s 13086.904us 1 1 100.00
sec_cm_intersig_mubi 2 2 100.00
entropy_src_rng 57.000s 13086.904us 1 1 100.00
entropy_src_fw_ov 64.000s 14198.247us 1 1 100.00
sec_cm_main_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 1.000s 118.503us 1 1 100.00
entropy_src_sec_cm 2.000s 278.497us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 2 2 100.00
entropy_src_functional_errors 1.000s 118.503us 1 1 100.00
entropy_src_sec_cm 2.000s 278.497us 1 1 100.00
sec_cm_rng_bkgn_chk 1 1 100.00
entropy_src_rng 57.000s 13086.904us 1 1 100.00
sec_cm_fifo_ctr_redun 2 2 100.00
entropy_src_functional_errors 1.000s 118.503us 1 1 100.00
entropy_src_sec_cm 2.000s 278.497us 1 1 100.00
sec_cm_ctr_redun 2 2 100.00
entropy_src_functional_errors 1.000s 118.503us 1 1 100.00
entropy_src_sec_cm 2.000s 278.497us 1 1 100.00
sec_cm_ctr_local_esc 1 1 100.00
entropy_src_functional_errors 1.000s 118.503us 1 1 100.00
sec_cm_esfinal_rdata_bus_consistency 1 1 100.00
entropy_src_functional_alerts 3.000s 667.202us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
entropy_src_tl_intg_err 3.000s 124.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
external_health_tests 1 1 100.00
entropy_src_rng_with_xht_rsps 47.000s 13193.757us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
entropy_src_stress_all_with_rand_reset 6.000s 503.439us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (entropy_src_scoreboard.sv:1663) scoreboard [scoreboard] invalid csr: entropy_src_reg_block.extht_lo_threshold 1 test run
entropy_src_stress_all_with_rand_reset 90382421720642035465595131172437893187149849726655330471608333638774243564627 323
UVM_INFO @ 503438713 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror alert_fail_counts 1 test run
entropy_src_csr_mem_rw_with_rand_reset 19650047440034704974379225480975685040107242569005319788983861431589776095047 113
UVM_INFO @ 5905414 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---