Simulation Results: flash_ctrl

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.65 %
  • code
  • 94.12 %
  • assert
  • 96.94 %
  • func
  • 95.88 %
  • line
  • 96.01 %
  • branch
  • 97.25 %
  • cond
  • 93.63 %
  • toggle
  • 97.99 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 48.290s 25.872us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 13.150s 56.189us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 23.590s 240.262us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 7.270s 595.599us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 57.410s 4245.586us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 28.950s 5140.544us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.510s 220.429us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 7.270s 595.599us 1 1 100.00
flash_ctrl_csr_aliasing 28.950s 5140.544us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 6.020s 43.834us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 6.300s 64.319us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 13.990s 28.724us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 36.760s 90.524us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1122.010s 83941.709us 1 1 100.00
flash_ctrl_hw_rma_reset 581.650s 80151.186us 1 1 100.00
flash_ctrl_lcmgr_intg 8.990s 23.582us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1016.220s 305870.526us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 154.840s 2864.898us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 7.340s 46.394us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 1813.120s 997416.238us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 50.150s 3077.070us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 16.130s 62.566us 1 1 100.00
flash_ctrl_rw_evict_all_en 14.310s 88.248us 1 1 100.00
flash_ctrl_re_evict 18.580s 145.504us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 256.040s 2816.217us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 256.040s 2816.217us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 264.080s 6687.049us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 15.110s 847.049us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 338.380s 396.511us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 424.120s 84978.845us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 348.990s 926.110us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 954.510s 13795.634us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 8.040s 79.233us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 166.000s 2448.280us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 10.140s 206.552us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.680s 30.578us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 571.870s 346.569us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 103.420s 2357.981us 1 1 100.00
flash_ctrl_otp_reset 58.800s 112.143us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1122.010s 83941.709us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 88.090s 3472.210us 1 1 100.00
flash_ctrl_intr_wr 62.520s 5916.384us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 161.150s 13316.495us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 110.290s 87566.026us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 44.070s 4552.064us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 37.010s 1962.066us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 16.880s 31.505us 1 1 100.00
flash_ctrl_ro_derr 104.500s 3168.840us 1 1 100.00
flash_ctrl_rw_derr 170.800s 3714.584us 1 1 100.00
flash_ctrl_derr_detect 102.360s 718.216us 1 1 100.00
flash_ctrl_integrity 338.980s 20314.707us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 11.310s 55.264us 1 1 100.00
flash_ctrl_ro_serr 99.970s 4468.378us 1 1 100.00
flash_ctrl_rw_serr 126.180s 1509.635us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 34.610s 635.158us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 37.060s 802.905us 1 1 100.00
scramble 5 5 100.00
flash_ctrl_wo 100.220s 2811.519us 1 1 100.00
flash_ctrl_write_word_sweep 7.390s 44.778us 1 1 100.00
flash_ctrl_read_word_sweep 7.010s 56.197us 1 1 100.00
flash_ctrl_ro 91.920s 3727.959us 1 1 100.00
flash_ctrl_rw 406.520s 4844.366us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 21.130s 757.047us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 642.370s 805304.366us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 18.480s 10154.068us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.270s 79.645us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 9.060s 139.835us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.060s 142.474us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.060s 142.474us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 23.590s 240.262us 1 1 100.00
flash_ctrl_csr_rw 7.270s 595.599us 1 1 100.00
flash_ctrl_csr_aliasing 28.950s 5140.544us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.580s 247.024us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 23.590s 240.262us 1 1 100.00
flash_ctrl_csr_rw 7.270s 595.599us 1 1 100.00
flash_ctrl_csr_aliasing 28.950s 5140.544us 1 1 100.00
flash_ctrl_same_csr_outstanding 9.580s 247.024us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 29.280s 27.772us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 29.280s 27.772us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 29.280s 27.772us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 29.280s 27.772us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 31.880s 329.984us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1821.140s 1464.678us 1 1 100.00
flash_ctrl_tl_intg_err 210.500s 341.782us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 210.500s 341.782us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 210.500s 341.782us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 16.850s 71.243us 1 1 100.00
flash_ctrl_wr_intg 7.710s 82.123us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 48.290s 25.872us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 58.800s 112.143us 1 1 100.00
flash_ctrl_disable 10.140s 206.552us 1 1 100.00
flash_ctrl_sec_info_access 44.870s 7000.578us 1 1 100.00
flash_ctrl_connect 5.680s 30.578us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.150s 42.325us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.270s 595.599us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 29.280s 27.772us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.270s 595.599us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 29.280s 27.772us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 7.270s 595.599us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 29.280s 27.772us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 10.140s 206.552us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 16.850s 71.243us 1 1 100.00
flash_ctrl_access_after_disable 6.150s 22.494us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 14.990s 28.692us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 10.140s 206.552us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 15.110s 847.049us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 406.520s 4844.366us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 126.180s 1509.635us 1 1 100.00
flash_ctrl_rw_derr 170.800s 3714.584us 1 1 100.00
flash_ctrl_integrity 338.980s 20314.707us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1122.010s 83941.709us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1821.140s 1464.678us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1821.140s 1464.678us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1821.140s 1464.678us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1821.140s 1464.678us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 13.950s 894.643us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 7.070s 40.480us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 10.260s 22.131us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1821.140s 1464.678us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1821.140s 1464.678us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1821.140s 1464.678us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 21.660s 87.059us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 211.560s 991.412us 1 1 100.00