Simulation Results: hmac

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 79.47 %
  • code
  • 97.73 %
  • assert
  • 97.16 %
  • func
  • 43.53 %
  • line
  • 99.69 %
  • branch
  • 99.01 %
  • cond
  • 95.84 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 4.140s 1104.904us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.750s 16.835us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.970s 105.014us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.870s 3821.939us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.070s 216.686us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 413.740s 733968.215us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.970s 105.014us 1 1 100.00
hmac_csr_aliasing 4.070s 216.686us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 49.200s 3128.513us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 3.070s 75.822us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 217.770s 38779.372us 1 1 100.00
hmac_test_sha384_vectors 20.760s 299.733us 1 1 100.00
hmac_test_sha512_vectors 20.780s 1182.469us 1 1 100.00
hmac_test_hmac256_vectors 5.890s 887.739us 1 1 100.00
hmac_test_hmac384_vectors 7.360s 1188.862us 1 1 100.00
hmac_test_hmac512_vectors 11.280s 429.411us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 5.290s 183.195us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 327.780s 43765.951us 1 1 100.00
error 1 1 100.00
hmac_error 111.130s 57220.111us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 97.170s 9880.212us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 4.140s 1104.904us 1 1 100.00
hmac_long_msg 49.200s 3128.513us 1 1 100.00
hmac_back_pressure 3.070s 75.822us 1 1 100.00
hmac_datapath_stress 327.780s 43765.951us 1 1 100.00
hmac_burst_wr 5.290s 183.195us 1 1 100.00
hmac_stress_all 103.360s 6594.380us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 4.140s 1104.904us 1 1 100.00
hmac_long_msg 49.200s 3128.513us 1 1 100.00
hmac_back_pressure 3.070s 75.822us 1 1 100.00
hmac_datapath_stress 327.780s 43765.951us 1 1 100.00
hmac_wipe_secret 97.170s 9880.212us 1 1 100.00
hmac_test_sha256_vectors 217.770s 38779.372us 1 1 100.00
hmac_test_sha384_vectors 20.760s 299.733us 1 1 100.00
hmac_test_sha512_vectors 20.780s 1182.469us 1 1 100.00
hmac_test_hmac256_vectors 5.890s 887.739us 1 1 100.00
hmac_test_hmac384_vectors 7.360s 1188.862us 1 1 100.00
hmac_test_hmac512_vectors 11.280s 429.411us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 4.140s 1104.904us 1 1 100.00
hmac_long_msg 49.200s 3128.513us 1 1 100.00
hmac_back_pressure 3.070s 75.822us 1 1 100.00
hmac_datapath_stress 327.780s 43765.951us 1 1 100.00
hmac_burst_wr 5.290s 183.195us 1 1 100.00
hmac_error 111.130s 57220.111us 1 1 100.00
hmac_wipe_secret 97.170s 9880.212us 1 1 100.00
hmac_test_sha256_vectors 217.770s 38779.372us 1 1 100.00
hmac_test_sha384_vectors 20.760s 299.733us 1 1 100.00
hmac_test_sha512_vectors 20.780s 1182.469us 1 1 100.00
hmac_test_hmac256_vectors 5.890s 887.739us 1 1 100.00
hmac_test_hmac384_vectors 7.360s 1188.862us 1 1 100.00
hmac_test_hmac512_vectors 11.280s 429.411us 1 1 100.00
hmac_stress_all 103.360s 6594.380us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 103.360s 6594.380us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.650s 11.637us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.680s 14.079us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.630s 77.000us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.630s 77.000us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.750s 16.835us 1 1 100.00
hmac_csr_rw 0.970s 105.014us 1 1 100.00
hmac_csr_aliasing 4.070s 216.686us 1 1 100.00
hmac_same_csr_outstanding 1.320s 209.786us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.750s 16.835us 1 1 100.00
hmac_csr_rw 0.970s 105.014us 1 1 100.00
hmac_csr_aliasing 4.070s 216.686us 1 1 100.00
hmac_same_csr_outstanding 1.320s 209.786us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.860s 75.703us 1 1 100.00
hmac_tl_intg_err 1.810s 99.071us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.810s 99.071us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 4.140s 1104.904us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.390s 102.568us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 126.940s 3053.810us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.900s 37.665us 1 1 100.00