Simulation Results

Simulation Results: i2c

07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
86.73 %

code
81.13 %

assert
96.19 %

func
82.88 %

line
96.38 %

branch
92.26 %

cond
84.78 %

toggle
88.19 %

FSM
44.05 %

Validation stages

V1		100.00%
V2		90.24%
V2S		100.00%
V3		0.00%

7/7 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_smoke				1	1	100.00
	i2c_host_smoke	24.600s	9544.303us	1	1	100.00
target_smoke				1	1	100.00
	i2c_target_smoke	8.100s	2018.270us	1	1	100.00
csr_hw_reset				1	1	100.00
	i2c_csr_hw_reset	0.960s	17.632us	1	1	100.00
csr_rw				1	1	100.00
	i2c_csr_rw	0.740s	79.618us	1	1	100.00
csr_bit_bash				1	1	100.00
	i2c_csr_bit_bash	4.110s	642.548us	1	1	100.00
csr_aliasing				1	1	100.00
	i2c_csr_aliasing	1.400s	60.131us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	i2c_csr_mem_rw_with_rand_reset	1.210s	54.104us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	i2c_csr_rw	0.740s	79.618us	1	1	100.00
	i2c_csr_aliasing	1.400s	60.131us	1	1	100.00

37/41 passed

90.24 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
host_error_intr				0	1	0.00
	i2c_host_error_intr	0.920s	108.331us	0	1	0.00
host_stress_all				0	1	0.00
	i2c_host_stress_all	325.760s	17869.334us	0	1	0.00
host_maxperf				1	1	100.00
	i2c_host_perf	10.360s	5142.699us	1	1	100.00
host_override				1	1	100.00
	i2c_host_override	0.990s	18.552us	1	1	100.00
host_fifo_watermark				1	1	100.00
	i2c_host_fifo_watermark	58.270s	16814.035us	1	1	100.00
host_fifo_overflow				1	1	100.00
	i2c_host_fifo_overflow	35.560s	1849.356us	1	1	100.00
host_fifo_reset				3	3	100.00
	i2c_host_fifo_reset_fmt	1.050s	341.549us	1	1	100.00
	i2c_host_fifo_fmt_empty	7.350s	440.039us	1	1	100.00
	i2c_host_fifo_reset_rx	4.220s	1378.191us	1	1	100.00
host_fifo_full				1	1	100.00
	i2c_host_fifo_full	32.570s	7684.214us	1	1	100.00
host_timeout				1	1	100.00
	i2c_host_stretch_timeout	30.300s	4952.563us	1	1	100.00
i2c_host_mode_toggle				0	1	0.00
	i2c_host_mode_toggle	1.320s	77.160us	0	1	0.00
target_glitch				0	1	0.00
	i2c_target_glitch	2.020s	1870.742us	0	1	0.00
target_stress_all				1	1	100.00
	i2c_target_stress_all	198.480s	23173.077us	1	1	100.00
target_maxperf				1	1	100.00
	i2c_target_perf	3.540s	555.234us	1	1	100.00
target_fifo_empty				2	2	100.00
	i2c_target_stress_rd	14.110s	1991.608us	1	1	100.00
	i2c_target_intr_smoke	4.590s	1857.925us	1	1	100.00
target_fifo_reset				2	2	100.00
	i2c_target_fifo_reset_acq	1.180s	127.841us	1	1	100.00
	i2c_target_fifo_reset_tx	1.370s	192.338us	1	1	100.00
target_fifo_full				3	3	100.00
	i2c_target_stress_wr	32.340s	22838.761us	1	1	100.00
	i2c_target_stress_rd	14.110s	1991.608us	1	1	100.00
	i2c_target_intr_stress_wr	67.500s	19962.730us	1	1	100.00
target_timeout				1	1	100.00
	i2c_target_timeout	4.690s	7532.494us	1	1	100.00
target_clock_stretch				1	1	100.00
	i2c_target_stretch	5.770s	1557.703us	1	1	100.00
bad_address				1	1	100.00
	i2c_target_bad_addr	4.190s	1056.347us	1	1	100.00
target_mode_glitch				1	1	100.00
	i2c_target_hrst	1.520s	488.935us	1	1	100.00
target_fifo_watermark				2	2	100.00
	i2c_target_fifo_watermarks_acq	1.970s	1693.462us	1	1	100.00
	i2c_target_fifo_watermarks_tx	1.550s	476.266us	1	1	100.00
host_mode_config_perf				2	2	100.00
	i2c_host_perf	10.360s	5142.699us	1	1	100.00
	i2c_host_perf_precise	8.380s	6455.212us	1	1	100.00
host_mode_clock_stretching				1	1	100.00
	i2c_host_stretch_timeout	30.300s	4952.563us	1	1	100.00
target_mode_tx_stretch_ctrl				1	1	100.00
	i2c_target_tx_stretch_ctrl	1.730s	100.425us	1	1	100.00
target_mode_nack_generation				3	3	100.00
	i2c_target_nack_acqfull	1.960s	815.142us	1	1	100.00
	i2c_target_nack_acqfull_addr	1.720s	2021.506us	1	1	100.00
	i2c_target_nack_txstretch	1.330s	159.760us	1	1	100.00
host_mode_halt_on_nak				1	1	100.00
	i2c_host_may_nack	5.940s	1903.322us	1	1	100.00
target_mode_smbus_maxlen				1	1	100.00
	i2c_target_smbus_maxlen	1.830s	463.233us	1	1	100.00
alert_test				1	1	100.00
	i2c_alert_test	0.840s	30.146us	1	1	100.00
intr_test				1	1	100.00
	i2c_intr_test	0.960s	34.795us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	i2c_tl_errors	1.390s	292.913us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	i2c_tl_errors	1.390s	292.913us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	i2c_csr_hw_reset	0.960s	17.632us	1	1	100.00
	i2c_csr_rw	0.740s	79.618us	1	1	100.00
	i2c_csr_aliasing	1.400s	60.131us	1	1	100.00
	i2c_same_csr_outstanding	1.350s	298.361us	1	1	100.00
tl_d_partial_access				4	4	100.00
	i2c_csr_hw_reset	0.960s	17.632us	1	1	100.00
	i2c_csr_rw	0.740s	79.618us	1	1	100.00
	i2c_csr_aliasing	1.400s	60.131us	1	1	100.00
	i2c_same_csr_outstanding	1.350s	298.361us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	i2c_tl_intg_err	1.690s	305.997us	1	1	100.00
	i2c_sec_cm	0.930s	56.041us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	i2c_tl_intg_err	1.690s	305.997us	1	1	100.00

0/3 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Total
host_stress_all_with_rand_reset				1
	i2c_host_stress_all_with_rand_reset	9.380s	726.077us	1
target_error_intr				1
	i2c_target_unexp_stop	2.050s	366.601us	1
target_stress_all_with_rand_reset				1
	i2c_target_stress_all_with_rand_reset	7.380s	826.211us	1

Error Messages

	Test	seed	line	log context
UVM_ERROR sequencer [sequencer] Get_next_item called twice without item_done or get in between				2 test runs
	i2c_host_error_intr	103428961142552063125641041615100778069437018187551346882086157376202879844294	96	UVM_INFO @ 108331223 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	i2c_host_stress_all	107358069088235618614465407267721705127951242506074043353384910872778420243389	126	UVM_INFO @ 17869333871 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR sequencer [sequencer] get_next_item/try_next_item called twice without item_done or get in between				1 test run
	i2c_target_glitch	85738551136945191505666535623316683262802172617662073253139332154999582244776	84	UVM_INFO @ 1870741692 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '($stable(tx_fifo_wvalid_i) && $stable(tx_fifo_wdata_i))'				1 test run
	i2c_target_unexp_stop	64461459470829434092047592422411534594574408461311689003187244293543940642241	79	UVM_ERROR @ 366601023 ps: (i2c_fifos.sv:318) [ASSERT FAILED] TxWriteStableBeforeHandshake_A UVM_INFO @ 366601023 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [i2c_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	i2c_host_stress_all_with_rand_reset	41593812935058300610399963693187791395981360294455287072878050753580090296774	88	UVM_INFO @ 726076898 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1199) [i2c_common_vseq] Check failed (cfg.can_reset_with_csr_accesses \|\| !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.				1 test run
	i2c_target_stress_all_with_rand_reset	32650383164004706642496967019167423902965459027560941532816372071017288609424	98	UVM_INFO @ 826211419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (i2c_scoreboard.sv:716) [scoreboard] controller_mode_rd_obs_fifo item uncompared:				1 test run
	i2c_host_mode_toggle	115101779154284308289088512856229413943796431234709740757007447290120659997940	85	---------------------------------------------------- Name Type Size Value ---------------------------------------------------- mon_dut_item i2c_item - @26477