| V1 |
|
100.00% |
| V2 |
|
94.74% |
| V2S |
|
90.91% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| keymgr_smoke | 2.170s | 64.445us | 1 | 1 | 100.00 | |
| random | 1 | 1 | 100.00 | |||
| keymgr_random | 3.740s | 498.207us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| keymgr_csr_hw_reset | 1.030s | 337.790us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| keymgr_csr_rw | 0.860s | 12.931us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| keymgr_csr_bit_bash | 9.800s | 811.179us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| keymgr_csr_aliasing | 3.090s | 71.028us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| keymgr_csr_mem_rw_with_rand_reset | 2.310s | 234.850us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| keymgr_csr_rw | 0.860s | 12.931us | 1 | 1 | 100.00 | |
| keymgr_csr_aliasing | 3.090s | 71.028us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| cfgen_during_op | 1 | 1 | 100.00 | |||
| keymgr_cfg_regwen | 10.580s | 331.701us | 1 | 1 | 100.00 | |
| sideload | 4 | 4 | 100.00 | |||
| keymgr_sideload | 1.690s | 96.351us | 1 | 1 | 100.00 | |
| keymgr_sideload_kmac | 1.650s | 52.384us | 1 | 1 | 100.00 | |
| keymgr_sideload_aes | 2.250s | 110.160us | 1 | 1 | 100.00 | |
| keymgr_sideload_otbn | 4.500s | 222.725us | 1 | 1 | 100.00 | |
| direct_to_disabled_state | 1 | 1 | 100.00 | |||
| keymgr_direct_to_disabled | 2.390s | 211.571us | 1 | 1 | 100.00 | |
| lc_disable | 0 | 1 | 0.00 | |||
| keymgr_lc_disable | 1.410s | 27.479us | 0 | 1 | 0.00 | |
| kmac_error_response | 1 | 1 | 100.00 | |||
| keymgr_kmac_rsp_err | 3.740s | 172.868us | 1 | 1 | 100.00 | |
| invalid_sw_input | 1 | 1 | 100.00 | |||
| keymgr_sw_invalid_input | 4.320s | 526.837us | 1 | 1 | 100.00 | |
| invalid_hw_input | 1 | 1 | 100.00 | |||
| keymgr_hwsw_invalid_input | 2.550s | 60.332us | 1 | 1 | 100.00 | |
| sync_async_fault_cross | 1 | 1 | 100.00 | |||
| keymgr_sync_async_fault_cross | 2.710s | 247.920us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| keymgr_stress_all | 3.920s | 223.380us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| keymgr_intr_test | 0.860s | 21.748us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| keymgr_alert_test | 0.830s | 38.272us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| keymgr_tl_errors | 2.660s | 428.693us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| keymgr_tl_errors | 2.660s | 428.693us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| keymgr_csr_hw_reset | 1.030s | 337.790us | 1 | 1 | 100.00 | |
| keymgr_csr_rw | 0.860s | 12.931us | 1 | 1 | 100.00 | |
| keymgr_csr_aliasing | 3.090s | 71.028us | 1 | 1 | 100.00 | |
| keymgr_same_csr_outstanding | 1.580s | 419.140us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| keymgr_csr_hw_reset | 1.030s | 337.790us | 1 | 1 | 100.00 | |
| keymgr_csr_rw | 0.860s | 12.931us | 1 | 1 | 100.00 | |
| keymgr_csr_aliasing | 3.090s | 71.028us | 1 | 1 | 100.00 | |
| keymgr_same_csr_outstanding | 1.580s | 419.140us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| sec_cm_additional_check | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| tl_intg_err | 2 | 2 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| keymgr_tl_intg_err | 7.180s | 246.038us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors | 3.630s | 174.535us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors | 3.630s | 174.535us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors | 3.630s | 174.535us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors | 3.630s | 174.535us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors_with_csr_rw | 9.260s | 815.961us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| prim_fsm_check | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| keymgr_tl_intg_err | 7.180s | 246.038us | 1 | 1 | 100.00 | |
| sec_cm_config_shadow | 1 | 1 | 100.00 | |||
| keymgr_shadow_reg_errors | 3.630s | 174.535us | 1 | 1 | 100.00 | |
| sec_cm_op_config_regwen | 1 | 1 | 100.00 | |||
| keymgr_cfg_regwen | 10.580s | 331.701us | 1 | 1 | 100.00 | |
| sec_cm_reseed_config_regwen | 2 | 2 | 100.00 | |||
| keymgr_random | 3.740s | 498.207us | 1 | 1 | 100.00 | |
| keymgr_csr_rw | 0.860s | 12.931us | 1 | 1 | 100.00 | |
| sec_cm_sw_binding_config_regwen | 2 | 2 | 100.00 | |||
| keymgr_random | 3.740s | 498.207us | 1 | 1 | 100.00 | |
| keymgr_csr_rw | 0.860s | 12.931us | 1 | 1 | 100.00 | |
| sec_cm_max_key_ver_config_regwen | 2 | 2 | 100.00 | |||
| keymgr_random | 3.740s | 498.207us | 1 | 1 | 100.00 | |
| keymgr_csr_rw | 0.860s | 12.931us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 0 | 1 | 0.00 | |||
| keymgr_lc_disable | 1.410s | 27.479us | 0 | 1 | 0.00 | |
| sec_cm_constants_consistency | 1 | 1 | 100.00 | |||
| keymgr_hwsw_invalid_input | 2.550s | 60.332us | 1 | 1 | 100.00 | |
| sec_cm_intersig_consistency | 1 | 1 | 100.00 | |||
| keymgr_hwsw_invalid_input | 2.550s | 60.332us | 1 | 1 | 100.00 | |
| sec_cm_hw_key_sw_noaccess | 1 | 1 | 100.00 | |||
| keymgr_random | 3.740s | 498.207us | 1 | 1 | 100.00 | |
| sec_cm_output_keys_ctrl_redun | 1 | 1 | 100.00 | |||
| keymgr_sideload_protect | 2.420s | 272.519us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| sec_cm_data_fsm_sparse | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_local_esc | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_consistency | 1 | 1 | 100.00 | |||
| keymgr_custom_cm | 4.820s | 138.729us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_fsm_global_esc | 0 | 1 | 0.00 | |||
| keymgr_lc_disable | 1.410s | 27.479us | 0 | 1 | 0.00 | |
| sec_cm_ctrl_ctr_redun | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| sec_cm_kmac_if_fsm_sparse | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| sec_cm_kmac_if_ctr_redun | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| sec_cm_kmac_if_cmd_ctrl_consistency | 1 | 1 | 100.00 | |||
| keymgr_custom_cm | 4.820s | 138.729us | 1 | 1 | 100.00 | |
| sec_cm_kmac_if_done_ctrl_consistency | 1 | 1 | 100.00 | |||
| keymgr_custom_cm | 4.820s | 138.729us | 1 | 1 | 100.00 | |
| sec_cm_reseed_ctr_redun | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| sec_cm_side_load_sel_ctrl_consistency | 1 | 1 | 100.00 | |||
| keymgr_custom_cm | 4.820s | 138.729us | 1 | 1 | 100.00 | |
| sec_cm_sideload_ctrl_fsm_sparse | 1 | 1 | 100.00 | |||
| keymgr_sec_cm | 5.000s | 1272.309us | 1 | 1 | 100.00 | |
| sec_cm_ctrl_key_integrity | 1 | 1 | 100.00 | |||
| keymgr_custom_cm | 4.820s | 138.729us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| keymgr_stress_all_with_rand_reset | 8.300s | 302.554us | 1 | 1 | 100.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_ERROR (keymgr_if.sv:557) [keymgr_if] Check failed {act_key.key[*], act_key.key[*]} !== keys_a_array[state][cdi][dest] (* [*] vs * [*]) AES key at state StOwnerKey for Attestation Aes | 1 test run | |||
| keymgr_lc_disable | 76942715192041385456664181667546560885034166811252706424409259849380060331332 | 253 |
UVM_INFO @ 27479419 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
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