Simulation Results

Simulation Results: kmac/unmasked

07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
79.48 %

code
65.77 %

assert
96.35 %

func
76.32 %

line
92.81 %

branch
87.43 %

cond
84.66 %

toggle
27.47 %

FSM
36.50 %

Validation stages

V1		100.00%
V2		68.97%
V2S		75.00%
V3		0.00%

8/8 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	kmac_smoke	19.100s	2505.435us	1	1	100.00
csr_hw_reset				1	1	100.00
	kmac_csr_hw_reset	1.220s	67.446us	1	1	100.00
csr_rw				1	1	100.00
	kmac_csr_rw	1.210s	52.101us	1	1	100.00
csr_bit_bash				1	1	100.00
	kmac_csr_bit_bash	12.760s	6945.059us	1	1	100.00
csr_aliasing				1	1	100.00
	kmac_csr_aliasing	3.910s	428.227us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	kmac_csr_mem_rw_with_rand_reset	1.770s	104.743us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	kmac_csr_rw	1.210s	52.101us	1	1	100.00
	kmac_csr_aliasing	3.910s	428.227us	1	1	100.00
mem_walk				1	1	100.00
	kmac_mem_walk	0.960s	11.236us	1	1	100.00
mem_partial_access				1	1	100.00
	kmac_mem_partial_access	1.480s	56.828us	1	1	100.00

20/29 passed

68.97 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
long_msg_and_output				1	1	100.00
	kmac_long_msg_and_output	2504.590s	314590.394us	1	1	100.00
burst_write				1	1	100.00
	kmac_burst_write	136.750s	10124.317us	1	1	100.00
test_vectors				8	8	100.00
	kmac_test_vectors_sha3_224	24.820s	3416.882us	1	1	100.00
	kmac_test_vectors_sha3_256	31.370s	2939.127us	1	1	100.00
	kmac_test_vectors_sha3_384	1261.960s	72130.542us	1	1	100.00
	kmac_test_vectors_sha3_512	13.980s	4423.107us	1	1	100.00
	kmac_test_vectors_shake_128	108.470s	6357.895us	1	1	100.00
	kmac_test_vectors_shake_256	2198.910s	436644.187us	1	1	100.00
	kmac_test_vectors_kmac	1.470s	41.856us	1	1	100.00
	kmac_test_vectors_kmac_xof	2.140s	148.380us	1	1	100.00
sideload				1	1	100.00
	kmac_sideload	36.450s	1759.105us	1	1	100.00
app				0	1	0.00
	kmac_app	0.940s	6.046us	0	1	0.00
app_with_partial_data				0	1	0.00
	kmac_app_with_partial_data	4.780s	323.430us	0	1	0.00
entropy_refresh				0	1	0.00
	kmac_entropy_refresh	11.440s	5160.385us	0	1	0.00
error				0	1	0.00
	kmac_error	8.550s	580.185us	0	1	0.00
key_error				0	1	0.00
	kmac_key_error	1.040s	87.935us	0	1	0.00
sideload_invalid				0	1	0.00
	kmac_sideload_invalid	0.910s	5.116us	0	1	0.00
edn_timeout_error				1	1	100.00
	kmac_edn_timeout_error	21.690s	2953.111us	1	1	100.00
entropy_mode_error				1	1	100.00
	kmac_entropy_mode_error	21.230s	5668.695us	1	1	100.00
entropy_ready_error				0	1	0.00
	kmac_entropy_ready_error	1.000s	18.213us	0	1	0.00
lc_escalation				0	1	0.00
	kmac_lc_escalation	1.470s	262.146us	0	1	0.00
stress_all				0	1	0.00
	kmac_stress_all	279.380s	12095.647us	0	1	0.00
intr_test				1	1	100.00
	kmac_intr_test	0.720s	41.225us	1	1	100.00
alert_test				1	1	100.00
	kmac_alert_test	0.800s	30.435us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	kmac_tl_errors	2.740s	138.663us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	kmac_tl_errors	2.740s	138.663us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	kmac_csr_hw_reset	1.220s	67.446us	1	1	100.00
	kmac_csr_rw	1.210s	52.101us	1	1	100.00
	kmac_csr_aliasing	3.910s	428.227us	1	1	100.00
	kmac_same_csr_outstanding	2.160s	115.018us	1	1	100.00
tl_d_partial_access				4	4	100.00
	kmac_csr_hw_reset	1.220s	67.446us	1	1	100.00
	kmac_csr_rw	1.210s	52.101us	1	1	100.00
	kmac_csr_aliasing	3.910s	428.227us	1	1	100.00
	kmac_same_csr_outstanding	2.160s	115.018us	1	1	100.00

V2S

6/8 passed

75.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
shadow_reg_update_error				1	1	100.00
	kmac_shadow_reg_errors	1.590s	53.276us	1	1	100.00
shadow_reg_read_clear_staged_value				1	1	100.00
	kmac_shadow_reg_errors	1.590s	53.276us	1	1	100.00
shadow_reg_storage_error				1	1	100.00
	kmac_shadow_reg_errors	1.590s	53.276us	1	1	100.00
shadowed_reset_glitch				1	1	100.00
	kmac_shadow_reg_errors	1.590s	53.276us	1	1	100.00
shadow_reg_update_error_with_csr_rw				1	1	100.00
	kmac_shadow_reg_errors_with_csr_rw	4.030s	934.971us	1	1	100.00
tl_intg_err				2	2	100.00
	kmac_sec_cm	35.830s	62727.368us	1	1	100.00
	kmac_tl_intg_err	3.100s	453.056us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	kmac_tl_intg_err	3.100s	453.056us	1	1	100.00
sec_cm_lc_escalate_en_intersig_mubi				0	1	0.00
	kmac_lc_escalation	1.470s	262.146us	0	1	0.00
sec_cm_sw_key_key_masking				1	1	100.00
	kmac_smoke	19.100s	2505.435us	1	1	100.00
sec_cm_key_sideload				1	1	100.00
	kmac_sideload	36.450s	1759.105us	1	1	100.00
sec_cm_cfg_shadowed_config_shadow				1	1	100.00
	kmac_shadow_reg_errors	1.590s	53.276us	1	1	100.00
sec_cm_fsm_sparse				1	1	100.00
	kmac_sec_cm	35.830s	62727.368us	1	1	100.00
sec_cm_ctr_redun				1	1	100.00
	kmac_sec_cm	35.830s	62727.368us	1	1	100.00
sec_cm_packer_ctr_redun				1	1	100.00
	kmac_sec_cm	35.830s	62727.368us	1	1	100.00
sec_cm_cfg_shadowed_config_regwen				1	1	100.00
	kmac_smoke	19.100s	2505.435us	1	1	100.00
sec_cm_fsm_global_esc				0	1	0.00
	kmac_lc_escalation	1.470s	262.146us	0	1	0.00
sec_cm_fsm_local_esc				1	1	100.00
	kmac_sec_cm	35.830s	62727.368us	1	1	100.00
sec_cm_absorbed_ctrl_mubi				0	1	0.00
	kmac_mubi	4.430s	367.966us	0	1	0.00
sec_cm_sw_cmd_ctrl_sparse				1	1	100.00
	kmac_smoke	19.100s	2505.435us	1	1	100.00

0/1 passed

0.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				0	1	0.00
	kmac_stress_all_with_rand_reset	16.490s	1104.336us	0	1	0.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [] vs []) Mismatch between unmasked_digest[] and dpi_digest[*]				8 test runs
	kmac_sideload_invalid	27463601124249461020890093144524159883392183518055315217093808122965728958246	76	UVM_INFO @ 5115813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_app	74676117115061026283181527364717915526909231112334507229097357204728270971433	77	UVM_INFO @ 6046268 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_app_with_partial_data	63352038406464270399835668712289984815382728246883489168250524956848605760845	83	UVM_INFO @ 323429586 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_entropy_refresh	25379198704497487061654831041238621002975226070738010417348231389481297156663	81	UVM_INFO @ 5160385337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_error	51266336296502982906808977963615952136755810698232057122147010162731009824981	83	UVM_INFO @ 580185245 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_entropy_ready_error	44552334297376258422589141348354245631490402307233105197260241628645987170587	77	UVM_INFO @ 18212524 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_lc_escalation	82655589759693940500731717114018442330642013858639363360484522418094079700813	82	UVM_INFO @ 262146103 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	kmac_stress_all	16083389509216969682317019367205109947774838102964101857627737392391588105794	306	UVM_INFO @ 12095646832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err)				1 test run
	kmac_mubi	14290022924954919811939109438780614695015949818733600805773215276069979108823	80	UVM_INFO @ 367966201 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))'				1 test run
	kmac_key_error	1889643143387252214536838341221035163281612768916259331011870865684273887822	78	UVM_ERROR @ 87935155 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A UVM_INFO @ 87935155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [kmac_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.				1 test run
	kmac_stress_all_with_rand_reset	18552730685035686579339099403987275812786160042787310589985900302905429405179	95	UVM_INFO @ 1104336251 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---