Simulation Results: lc_ctrl/volatile_unlock_disabled

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.26 %
  • code
  • 83.85 %
  • assert
  • 94.41 %
  • func
  • 92.53 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.08 %
  • toggle
  • 85.71 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.100s 129.228us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.140s 17.279us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.970s 24.160us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.880s 117.693us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.300s 73.651us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.580s 32.527us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.970s 24.160us 1 1 100.00
lc_ctrl_csr_aliasing 1.300s 73.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.630s 876.508us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.460s 1421.698us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 1.180s 14.538us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.480s 559.199us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.600s 672.967us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 9.230s 1603.344us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.600s 672.967us 1 1 100.00
lc_ctrl_prog_failure 2.480s 559.199us 1 1 100.00
lc_ctrl_errors 9.230s 1603.344us 1 1 100.00
lc_ctrl_security_escalation 6.610s 5723.951us 1 1 100.00
lc_ctrl_jtag_state_failure 32.350s 3173.736us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.510s 584.586us 1 1 100.00
lc_ctrl_jtag_errors 14.530s 1362.062us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 6.460s 2464.014us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.250s 3518.725us 1 1 100.00
lc_ctrl_jtag_prog_failure 3.510s 584.586us 1 1 100.00
lc_ctrl_jtag_errors 14.530s 1362.062us 1 1 100.00
lc_ctrl_jtag_access 1.100s 91.116us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.540s 2659.735us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 2.480s 106.262us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.340s 55.647us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 6.570s 4426.470us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.830s 1148.468us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.560s 46.584us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 4.480s 1097.069us 1 1 100.00
lc_ctrl_jtag_alert_test 1.130s 26.368us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.550s 1525.084us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.800s 15.244us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 250.080s 100023.295us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.860s 16.351us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.950s 180.286us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.950s 180.286us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.140s 17.279us 1 1 100.00
lc_ctrl_csr_rw 0.970s 24.160us 1 1 100.00
lc_ctrl_csr_aliasing 1.300s 73.651us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 71.267us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.140s 17.279us 1 1 100.00
lc_ctrl_csr_rw 0.970s 24.160us 1 1 100.00
lc_ctrl_csr_aliasing 1.300s 73.651us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 71.267us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 6.810s 1319.717us 1 1 100.00
lc_ctrl_tl_intg_err 1.440s 66.264us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.440s 66.264us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.460s 1421.698us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 672.967us 1 1 100.00
lc_ctrl_sec_cm 6.810s 1319.717us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 672.967us 1 1 100.00
lc_ctrl_sec_cm 6.810s 1319.717us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.600s 672.967us 1 1 100.00
lc_ctrl_sec_cm 6.810s 1319.717us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.600s 672.967us 1 1 100.00
lc_ctrl_sec_cm 6.810s 1319.717us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 672.967us 1 1 100.00
lc_ctrl_sec_cm 6.810s 1319.717us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 672.967us 1 1 100.00
lc_ctrl_sec_cm 6.810s 1319.717us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.600s 672.967us 1 1 100.00
lc_ctrl_sec_cm 6.810s 1319.717us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.600s 672.967us 1 1 100.00
lc_ctrl_sec_cm 6.810s 1319.717us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.610s 5723.951us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.630s 876.508us 1 1 100.00
lc_ctrl_jtag_state_post_trans 14.250s 3518.725us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.560s 523.687us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 10.560s 523.687us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 7.630s 815.480us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.770s 773.362us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.770s 773.362us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 51.470s 4389.535us 1 1 100.00