Simulation Results: lc_ctrl/volatile_unlock_enabled

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.67 %
  • code
  • 83.74 %
  • assert
  • 94.69 %
  • func
  • 93.59 %
  • line
  • 97.09 %
  • branch
  • 93.37 %
  • cond
  • 78.92 %
  • toggle
  • 85.78 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.470s 221.697us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.790s 107.472us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.780s 59.432us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.200s 37.935us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 50.743us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.960s 54.775us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.780s 59.432us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 50.743us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.780s 208.682us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.390s 356.274us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.720s 44.158us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.380s 120.573us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.610s 857.565us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 12.210s 2986.881us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.610s 857.565us 1 1 100.00
lc_ctrl_prog_failure 3.380s 120.573us 1 1 100.00
lc_ctrl_errors 12.210s 2986.881us 1 1 100.00
lc_ctrl_security_escalation 3.830s 866.606us 1 1 100.00
lc_ctrl_jtag_state_failure 25.870s 14882.296us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.860s 87.216us 1 1 100.00
lc_ctrl_jtag_errors 19.410s 4797.729us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.710s 417.699us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.160s 449.228us 1 1 100.00
lc_ctrl_jtag_prog_failure 1.860s 87.216us 1 1 100.00
lc_ctrl_jtag_errors 19.410s 4797.729us 1 1 100.00
lc_ctrl_jtag_access 7.510s 4459.778us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 13.840s 1291.791us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.290s 92.862us 1 1 100.00
lc_ctrl_jtag_csr_rw 0.990s 39.303us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 3.550s 2399.430us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 6.170s 11469.030us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.270s 33.560us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.540s 86.589us 1 1 100.00
lc_ctrl_jtag_alert_test 0.930s 50.052us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 2.130s 171.534us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 1.010s 88.568us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 121.750s 27066.010us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 1.150s 258.036us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 2.600s 80.236us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 2.600s 80.236us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.790s 107.472us 1 1 100.00
lc_ctrl_csr_rw 0.780s 59.432us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 50.743us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.140s 110.195us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.790s 107.472us 1 1 100.00
lc_ctrl_csr_rw 0.780s 59.432us 1 1 100.00
lc_ctrl_csr_aliasing 1.180s 50.743us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.140s 110.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.570s 525.571us 1 1 100.00
lc_ctrl_tl_intg_err 2.910s 113.823us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.910s 113.823us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.390s 356.274us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.610s 857.565us 1 1 100.00
lc_ctrl_sec_cm 7.570s 525.571us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.610s 857.565us 1 1 100.00
lc_ctrl_sec_cm 7.570s 525.571us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.610s 857.565us 1 1 100.00
lc_ctrl_sec_cm 7.570s 525.571us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.610s 857.565us 1 1 100.00
lc_ctrl_sec_cm 7.570s 525.571us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.610s 857.565us 1 1 100.00
lc_ctrl_sec_cm 7.570s 525.571us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.610s 857.565us 1 1 100.00
lc_ctrl_sec_cm 7.570s 525.571us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.610s 857.565us 1 1 100.00
lc_ctrl_sec_cm 7.570s 525.571us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.610s 857.565us 1 1 100.00
lc_ctrl_sec_cm 7.570s 525.571us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 3.830s 866.606us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.780s 208.682us 1 1 100.00
lc_ctrl_jtag_state_post_trans 9.160s 449.228us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.370s 328.209us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 5.370s 328.209us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 6.550s 1195.386us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.040s 262.989us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.040s 262.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
lc_ctrl_stress_all_with_rand_reset 25.080s 1349.151us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [lc_ctrl_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
lc_ctrl_stress_all_with_rand_reset 71097942373918437739964992610834579017901562458694576749745528492663575413208 3792
UVM_INFO @ 1349150920 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---