Simulation Results: otbn

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.86 %
  • code
  • 80.65 %
  • assert
  • 87.58 %
  • func
  • 95.34 %
  • block
  • 97.74 %
  • line
  • 97.91 %
  • branch
  • 82.03 %
  • toggle
  • 79.27 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
100.00%
V2S
92.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 191.243us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 129.884us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 36.000s 19.348us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 35.000s 13.163us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 37.000s 180.667us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 36.000s 69.966us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 39.000s 500.962us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 35.000s 13.163us 1 1 100.00
otbn_csr_aliasing 36.000s 69.966us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 88.000s 46485.724us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 45.000s 1327.169us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 23.000s 67.361us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 49.000s 1001.788us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 39.000s 1561.596us 1 1 100.00
stress_all 1 1 100.00
otbn_stress_all 41.000s 270.390us 1 1 100.00
lc_escalation 1 1 100.00
otbn_escalate 38.000s 41.800us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 6.000s 59.204us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 23.000s 65.510us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 36.000s 89.548us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 32.000s 25.612us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 110.094us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 110.094us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 36.000s 19.348us 1 1 100.00
otbn_csr_rw 35.000s 13.163us 1 1 100.00
otbn_csr_aliasing 36.000s 69.966us 1 1 100.00
otbn_same_csr_outstanding 4.000s 35.038us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 36.000s 19.348us 1 1 100.00
otbn_csr_rw 35.000s 13.163us 1 1 100.00
otbn_csr_aliasing 36.000s 69.966us 1 1 100.00
otbn_same_csr_outstanding 4.000s 35.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 39.000s 37.724us 1 1 100.00
otbn_dmem_err 46.000s 58.217us 1 1 100.00
internal_integrity 4 4 100.00
otbn_alu_bignum_mod_err 40.000s 59.193us 1 1 100.00
otbn_controller_ispr_rdata_err 42.000s 244.306us 1 1 100.00
otbn_mac_bignum_acc_err 33.000s 45.542us 1 1 100.00
otbn_urnd_err 9.000s 118.422us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 35.000s 26.020us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 24.000s 13.594us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 6.000s 62.029us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
otbn_tl_intg_err 20.000s 263.060us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 42.000s 962.403us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 191.243us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 46.000s 58.217us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 39.000s 37.724us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 20.000s 263.060us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 38.000s 41.800us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 39.000s 37.724us 1 1 100.00
otbn_dmem_err 46.000s 58.217us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 59.204us 1 1 100.00
otbn_illegal_mem_acc 35.000s 26.020us 1 1 100.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 129.884us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 39.000s 37.724us 1 1 100.00
otbn_dmem_err 46.000s 58.217us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 59.204us 1 1 100.00
otbn_illegal_mem_acc 35.000s 26.020us 1 1 100.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 38.000s 41.800us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 39.000s 37.724us 1 1 100.00
otbn_dmem_err 46.000s 58.217us 1 1 100.00
otbn_zero_state_err_urnd 6.000s 59.204us 1 1 100.00
otbn_illegal_mem_acc 35.000s 26.020us 1 1 100.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 129.884us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 37.000s 13.341us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 6.000s 44.472us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 38.000s 322.845us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 38.000s 322.845us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 20.128us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 10.000s 111.552us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
sec_cm_loop_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 7.579us 0 1 0.00
sec_cm_call_stack_addr_integrity 0 1 0.00
otbn_stack_addr_integ_chk 6.000s 7.579us 0 1 0.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 5.000s 16.993us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 129.884us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 129.884us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 129.884us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 39.000s 1561.596us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 129.884us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 129.884us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 9.000s 357.098us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 129.884us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 9.000s 48.019us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
otbn_stress_all_with_rand_reset 92.000s 2598.998us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 18.774us 1 1 100.00

Error Messages

   Test seed line log context
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_dv_otbn_env_*/otbn_insn_cnt_if.sv,21): Assertion InsnCntMatches_A has failed 1 test run
otbn_stack_addr_integ_chk 19915353661351044648591986043264794591631133725018688871566644586502726333733 111
UVM_ERROR @ 7578884 ps: (otbn_insn_cnt_if.sv:21) [ASSERT FAILED] InsnCntMatches_A
UVM_INFO @ 7578884 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 1 test run
otbn_sec_cm 79072978469346566023229882265695188144141364423241883572236399788974768035810 100
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv,211): (time 48019292 PS) Assertion tb.dut.u_otbn_core.gen_mai.u_otbn_mai.u_otbn_mask_accelerator.u_prim_fifo_sync_mask.gen_normal_fifo.depthShallNotExceedParamDepth has failed
UVM_ERROR @ 48019292 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 48019292 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---