Simulation Results: otp_ctrl

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.34 %
  • code
  • 78.25 %
  • assert
  • 94.88 %
  • func
  • 70.88 %
  • line
  • 88.55 %
  • branch
  • 83.50 %
  • cond
  • 90.29 %
  • toggle
  • 85.16 %
  • FSM
  • 43.75 %
Validation stages
V1
100.00%
V2
95.00%
V2S
88.89%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.310s 54.668us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 2.970s 397.123us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 2.640s 1451.989us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.750s 43.386us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 5.550s 595.333us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 4.530s 182.793us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.750s 68.161us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.750s 43.386us 1 1 100.00
otp_ctrl_csr_aliasing 4.530s 182.793us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.490s 59.741us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.170s 52.495us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 15.030s 815.999us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.520s 160.446us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 10.530s 2369.300us 1 1 100.00
otp_ctrl_check_fail 10.310s 1500.342us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 4.940s 1796.817us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 10.630s 781.325us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 11.780s 1457.516us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 11.310s 1148.962us 1 1 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 7.810s 1365.830us 1 1 100.00
otp_macro_errors 1 1 100.00
otp_ctrl_macro_errs 5.090s 387.020us 1 1 100.00
test_access 1 1 100.00
otp_ctrl_test_access 10.970s 1740.596us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 78.510s 6806.027us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.110s 568.317us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.940s 159.604us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 4.700s 184.078us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 4.700s 184.078us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.640s 1451.989us 1 1 100.00
otp_ctrl_csr_rw 1.750s 43.386us 1 1 100.00
otp_ctrl_csr_aliasing 4.530s 182.793us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.630s 542.511us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 2.640s 1451.989us 1 1 100.00
otp_ctrl_csr_rw 1.750s 43.386us 1 1 100.00
otp_ctrl_csr_aliasing 4.530s 182.793us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.630s 542.511us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
otp_ctrl_tl_intg_err 12.560s 2373.722us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 12.560s 2373.722us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 2.970s 397.123us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 2.970s 397.123us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
sec_cm_part_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
otp_ctrl_macro_errs 5.090s 387.020us 1 1 100.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
sec_cm_part_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
otp_ctrl_macro_errs 5.090s 387.020us 1 1 100.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 7.860s 243.975us 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.520s 160.446us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 10.310s 1500.342us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 10.630s 781.325us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 10.630s 781.325us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 10.630s 781.325us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 10.630s 781.325us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 10.630s 781.325us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 2.970s 397.123us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 10.630s 781.325us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 2.970s 397.123us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 111.620s 19759.094us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 4.940s 1796.817us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 2.970s 397.123us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 2.970s 397.123us 1 1 100.00
sec_cm_macro_mem_integrity 1 1 100.00
otp_ctrl_macro_errs 5.090s 387.020us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 17.850s 7999.064us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 40.090s 2218.873us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 1 test run
otp_ctrl_check_fail 13137884715660219409845101491819398746485953489879957279868421688765293541739 7731
UVM_INFO @ 1500341863 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.intr_state 1 test run
otp_ctrl_stress_all_with_rand_reset 53733448311360066539066078671431546531436273350705003909246217206496073734472 15550
UVM_INFO @ 2218872571 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---