Simulation Results: pwrmgr

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.88 %
  • code
  • 91.16 %
  • assert
  • 98.96 %
  • func
  • 97.53 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.19 %
  • toggle
  • 91.15 %
  • FSM
  • 74.00 %
Validation stages
V1
100.00%
V2
80.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.610s 70.845us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.640s 61.059us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.690s 48.989us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.460s 278.496us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.050s 740.493us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.830s 57.033us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.690s 48.989us 1 1 100.00
pwrmgr_csr_aliasing 1.050s 740.493us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.940s 312.427us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.940s 312.427us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.850s 122.312us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 81.357us 1 1 100.00
reset 0 2 0.00
pwrmgr_reset 2.200s 1000.000us 0 1 0.00
pwrmgr_reset_invalid 0.750s 102.519us 0 1 0.00
main_power_glitch_reset 0 1 0.00
pwrmgr_reset 2.200s 1000.000us 0 1 0.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.750s 119.496us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.700s 429.413us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.760s 86.892us 1 1 100.00
stress_all 0 1 0.00
pwrmgr_stress_all 4.500s 11470.734us 0 1 0.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.670s 26.324us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.120s 198.938us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.120s 198.938us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.640s 61.059us 1 1 100.00
pwrmgr_csr_rw 0.690s 48.989us 1 1 100.00
pwrmgr_csr_aliasing 1.050s 740.493us 1 1 100.00
pwrmgr_same_csr_outstanding 0.820s 40.049us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.640s 61.059us 1 1 100.00
pwrmgr_csr_rw 0.690s 48.989us 1 1 100.00
pwrmgr_csr_aliasing 1.050s 740.493us 1 1 100.00
pwrmgr_same_csr_outstanding 0.820s 40.049us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.310s 215.885us 1 1 100.00
pwrmgr_sec_cm 0.900s 1440.301us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 0.900s 1440.301us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 0.900s 1440.301us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.310s 215.885us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.600s 1551.851us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.750s 119.496us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.480s 947.467us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.850s 75.052us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.680s 33.466us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 0.900s 1440.301us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 0.900s 1440.301us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 0.900s 1440.301us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.610s 30.377us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.680s 47.482us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.620s 115.949us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 48.989us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.690s 48.989us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.720s 330.806us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 4.040s 3531.810us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue 1 test run
pwrmgr_reset 63840537355077389977552295522260223847308071180448223822052988781513329546987 120
UVM_INFO @ 1000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Offending '((!clk_en) || status)' 1 test run
pwrmgr_escalation_timeout 109514613260049631987804073781448358948391255113534786639893947329420638093082 79
UVM_ERROR @ 330805979 ps: (clkmgr_pwrmgr_sva_if.sv:37) [ASSERT FAILED] StatusRise_A
UVM_INFO @ 330805979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_invalid_vseq.sv:55) [pwrmgr_reset_invalid_vseq] Timed out waiting for state DVWaitStrap 1 test run
pwrmgr_reset_invalid 53958495904801055698724004706090005515262652926704021638466082082263442795075 123
UVM_INFO @ 102518947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all 7170456683359406672448952131089467287629220488102068270822319921666741427137 552
UVM_INFO @ 11470734382 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---