Simulation Results: rom_ctrl/64kb

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.37 %
  • code
  • 95.56 %
  • assert
  • 96.66 %
  • func
  • 96.90 %
  • line
  • 99.46 %
  • branch
  • 99.27 %
  • cond
  • 97.47 %
  • toggle
  • 94.93 %
  • FSM
  • 86.67 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.820s 375.315us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 10.880s 1078.412us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.830s 289.111us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 6.060s 210.792us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 9.090s 3219.506us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.260s 2019.189us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.830s 289.111us 1 1 100.00
rom_ctrl_csr_aliasing 9.090s 3219.506us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 7.370s 4132.980us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.090s 383.882us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 10.490s 1928.306us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 40.670s 43868.876us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 14.290s 566.386us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 5.550s 727.512us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.530s 556.079us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.530s 556.079us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.880s 1078.412us 1 1 100.00
rom_ctrl_csr_rw 6.830s 289.111us 1 1 100.00
rom_ctrl_csr_aliasing 9.090s 3219.506us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.010s 1112.697us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 10.880s 1078.412us 1 1 100.00
rom_ctrl_csr_rw 6.830s 289.111us 1 1 100.00
rom_ctrl_csr_aliasing 9.090s 3219.506us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.010s 1112.697us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.080s 6864.664us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.640s 1605.776us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 458.290s 1120.699us 1 1 100.00
rom_ctrl_tl_intg_err 100.510s 848.145us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 458.290s 1120.699us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 458.290s 1120.699us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.080s 6864.664us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.080s 6864.664us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.080s 6864.664us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.080s 6864.664us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.080s 6864.664us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 458.290s 1120.699us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 458.290s 1120.699us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.820s 375.315us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.820s 375.315us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.820s 375.315us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 100.510s 848.145us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.080s 6864.664us 1 1 100.00
rom_ctrl_kmac_err_chk 14.290s 566.386us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.080s 6864.664us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.080s 6864.664us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 82.080s 6864.664us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.640s 1605.776us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 458.290s 1120.699us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 106.230s 14163.562us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 18893303718915499664522196217066896757622668905079242766553967801119961493636 79
UVM_INFO @ 1928305966 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---