Simulation Results: rstmgr

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.35 %
  • code
  • 99.37 %
  • assert
  • 98.66 %
  • func
  • 97.01 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.89 %
  • toggle
  • 99.24 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.080s 144.116us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.820s 124.160us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.870s 91.024us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.720s 699.948us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.440s 254.790us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.360s 183.235us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.870s 91.024us 1 1 100.00
rstmgr_csr_aliasing 1.440s 254.790us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.800s 191.749us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.720s 405.076us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.970s 158.314us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 5.850s 2452.292us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 5.850s 2452.292us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 5.850s 2452.292us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 5.850s 2452.292us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 5.000s 1636.428us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 1.020s 76.945us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.430s 506.953us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.430s 506.953us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.820s 124.160us 1 1 100.00
rstmgr_csr_rw 0.870s 91.024us 1 1 100.00
rstmgr_csr_aliasing 1.440s 254.790us 1 1 100.00
rstmgr_same_csr_outstanding 1.270s 262.607us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.820s 124.160us 1 1 100.00
rstmgr_csr_rw 0.870s 91.024us 1 1 100.00
rstmgr_csr_aliasing 1.440s 254.790us 1 1 100.00
rstmgr_same_csr_outstanding 1.270s 262.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 9.570s 8704.470us 1 1 100.00
rstmgr_tl_intg_err 1.520s 492.994us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 9.570s 8704.470us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 9.570s 8704.470us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.520s 492.994us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.990s 211.356us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.420s 1416.709us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 0.960s 302.163us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 9.570s 8704.470us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.870s 91.024us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.870s 91.024us 1 1 100.00