Simulation Results: rv_timer

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.52 %
  • code
  • 94.66 %
  • assert
  • 98.73 %
  • func
  • 96.18 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 78.66 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
66.67%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 0.830s 721.822us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.660s 66.961us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.580s 54.961us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.250s 301.723us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.920s 37.905us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.870s 41.507us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.580s 54.961us 1 1 100.00
rv_timer_csr_aliasing 0.920s 37.905us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.630s 247.483us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.150s 787.342us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 3.050s 2573.035us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 3.050s 2573.035us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.990s 4577.705us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.550s 39.785us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.620s 94.710us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.810s 102.374us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.810s 102.374us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.660s 66.961us 1 1 100.00
rv_timer_csr_rw 0.580s 54.961us 1 1 100.00
rv_timer_csr_aliasing 0.920s 37.905us 1 1 100.00
rv_timer_same_csr_outstanding 0.750s 39.538us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.660s 66.961us 1 1 100.00
rv_timer_csr_rw 0.580s 54.961us 1 1 100.00
rv_timer_csr_aliasing 0.920s 37.905us 1 1 100.00
rv_timer_same_csr_outstanding 0.750s 39.538us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 0.830s 185.622us 1 1 100.00
rv_timer_tl_intg_err 1.080s 433.773us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.080s 433.773us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 1 1 100.00
rv_timer_min 0.590s 51.748us 1 1 100.00
max_value 0 1 0.00
rv_timer_max 1.250s 41.947us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 26.710s 16614.784us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 44767799818798870899303728435968346949063173345764728454050198198026948871203 75
UVM_INFO @ 41946722 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 1 test run
rv_timer_random_reset 47296933107015669594316767501610497523522875782301374624768470226964536414691 75
UVM_INFO @ 247482765 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---