Simulation Results: spi_device/1r1w

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 85.22 %
  • code
  • 90.63 %
  • assert
  • 95.40 %
  • func
  • 69.64 %
  • line
  • 98.86 %
  • branch
  • 98.21 %
  • cond
  • 95.70 %
  • toggle
  • 71.04 %
  • FSM
  • 89.36 %
Validation stages
V1
100.00%
V2
92.59%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_device_flash_and_tpm 292.320s 104335.022us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_device_csr_hw_reset 0.920s 89.120us 1 1 100.00
csr_rw 1 1 100.00
spi_device_csr_rw 2.210s 82.886us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_device_csr_bit_bash 24.030s 1556.783us 1 1 100.00
csr_aliasing 1 1 100.00
spi_device_csr_aliasing 11.050s 1360.926us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_device_csr_mem_rw_with_rand_reset 1.540s 64.836us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_device_csr_rw 2.210s 82.886us 1 1 100.00
spi_device_csr_aliasing 11.050s 1360.926us 1 1 100.00
mem_walk 1 1 100.00
spi_device_mem_walk 0.620s 28.688us 1 1 100.00
mem_partial_access 1 1 100.00
spi_device_mem_partial_access 1.350s 226.618us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 1 1 100.00
spi_device_csb_read 0.690s 28.493us 1 1 100.00
mem_parity 0 1 0.00
spi_device_mem_parity 0.930s 2.194us 0 1 0.00
mem_cfg 0 1 0.00
spi_device_ram_cfg 0.620s 3.554us 0 1 0.00
tpm_read 1 1 100.00
spi_device_tpm_rw 0.800s 55.126us 1 1 100.00
tpm_write 1 1 100.00
spi_device_tpm_rw 0.800s 55.126us 1 1 100.00
tpm_hw_reg 2 2 100.00
spi_device_tpm_read_hw_reg 5.130s 1438.423us 1 1 100.00
spi_device_tpm_sts_read 0.900s 878.205us 1 1 100.00
tpm_fully_random_case 1 1 100.00
spi_device_tpm_all 21.520s 17091.450us 1 1 100.00
pass_cmd_filtering 2 2 100.00
spi_device_pass_cmd_filtering 3.790s 774.735us 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
pass_addr_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.040s 22467.342us 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
pass_payload_translation 2 2 100.00
spi_device_pass_addr_payload_swap 5.040s 22467.342us 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
cmd_info_slots 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
cmd_read_status 2 2 100.00
spi_device_intercept 2.260s 339.184us 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
cmd_read_jedec 2 2 100.00
spi_device_intercept 2.260s 339.184us 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
cmd_read_sfdp 2 2 100.00
spi_device_intercept 2.260s 339.184us 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
cmd_fast_read 2 2 100.00
spi_device_intercept 2.260s 339.184us 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
cmd_read_pipeline 2 2 100.00
spi_device_intercept 2.260s 339.184us 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
flash_cmd_upload 1 1 100.00
spi_device_upload 3.250s 265.069us 1 1 100.00
mailbox_command 1 1 100.00
spi_device_mailbox 2.560s 314.172us 1 1 100.00
mailbox_cross_outside_command 1 1 100.00
spi_device_mailbox 2.560s 314.172us 1 1 100.00
mailbox_cross_inside_command 1 1 100.00
spi_device_mailbox 2.560s 314.172us 1 1 100.00
cmd_read_buffer 2 2 100.00
spi_device_flash_mode 11.170s 1788.906us 1 1 100.00
spi_device_read_buffer_direct 4.850s 1694.150us 1 1 100.00
cmd_dummy_cycle 2 2 100.00
spi_device_mailbox 2.560s 314.172us 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
quad_spi 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
dual_spi 1 1 100.00
spi_device_flash_all 34.940s 16244.039us 1 1 100.00
4b_3b_feature 1 1 100.00
spi_device_cfg_cmd 4.120s 291.983us 1 1 100.00
write_enable_disable 1 1 100.00
spi_device_cfg_cmd 4.120s 291.983us 1 1 100.00
flash_mode_ignore_cmds 1 1 100.00
spi_device_flash_mode_ignore_cmds 19.200s 1429.308us 1 1 100.00
TPM_with_flash_or_passthrough_mode 1 1 100.00
spi_device_flash_and_tpm 292.320s 104335.022us 1 1 100.00
tpm_and_flash_trans_with_min_inactive_time 1 1 100.00
spi_device_flash_and_tpm_min_idle 3.790s 778.753us 1 1 100.00
stress_all 1 1 100.00
spi_device_stress_all 394.760s 73222.794us 1 1 100.00
alert_test 1 1 100.00
spi_device_alert_test 0.830s 29.932us 1 1 100.00
intr_test 1 1 100.00
spi_device_intr_test 0.810s 14.991us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_device_tl_errors 2.810s 1930.585us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_device_tl_errors 2.810s 1930.585us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_device_csr_hw_reset 0.920s 89.120us 1 1 100.00
spi_device_csr_rw 2.210s 82.886us 1 1 100.00
spi_device_csr_aliasing 11.050s 1360.926us 1 1 100.00
spi_device_same_csr_outstanding 3.630s 390.128us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_device_csr_hw_reset 0.920s 89.120us 1 1 100.00
spi_device_csr_rw 2.210s 82.886us 1 1 100.00
spi_device_csr_aliasing 11.050s 1360.926us 1 1 100.00
spi_device_same_csr_outstanding 3.630s 390.128us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_device_sec_cm 0.840s 171.053us 1 1 100.00
spi_device_tl_intg_err 12.160s 704.800us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_device_tl_intg_err 12.160s 704.800us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) 1 test run
spi_device_mem_parity 33348041793957652579430121945641511374057820804410893442599428094272667376796 76
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR @ 1798183 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
UVM_ERROR @ 1798183 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[925])
Either the name is incorrect, or you may not have PLI/ACC visibility to that name
UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) 1 test run
spi_device_ram_cfg 96377884285717605688617728723542674056180348050548047746414323262476133618998 76
UVM_ERROR @ 1339508 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x3478dc [1101000111100011011100] vs 0x0 [0])
UVM_ERROR @ 1373508 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x2a20d7 [1010100010000011010111] vs 0x0 [0])
UVM_ERROR @ 1428508 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x636513 [11000110110010100010011] vs 0x0 [0])
UVM_ERROR @ 1492508 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5ebd52 [10111101011110101010010] vs 0x0 [0])