Simulation Results: sram_ctrl/main

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 94.83 %
  • code
  • 94.54 %
  • assert
  • 97.55 %
  • func
  • 92.40 %
  • block
  • 94.56 %
  • line
  • 95.06 %
  • branch
  • 91.26 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 4816.073us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 24.129us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.528us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 107.269us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 53.223us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 4345.516us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 46.528us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 53.223us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 93.000s 3440.817us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 42.000s 13436.933us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 19.000s 8381.833us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 220.000s 11802.069us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 163.000s 97450.252us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 8.000s 1732.934us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 28.000s 31996.460us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 23.000s 19746.051us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 4.000s 707.942us 1 1 100.00
sram_ctrl_partial_access_b2b 173.000s 47209.244us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 1320.418us 0 1 0.00
sram_ctrl_throughput_w_partial_write 3.000s 1991.231us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 709.055us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 16.000s 3113.343us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1356.570us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 338.000s 48691.885us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 22.571us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 33.149us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 33.149us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 24.129us 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.528us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 53.223us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.361us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 24.129us 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.528us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 53.223us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 15.361us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.000s 61379.339us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 3.000s 1254.705us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 195.333us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 3.000s 1254.705us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 195.333us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 16.000s 3113.343us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 16.000s 3113.343us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 46.528us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 23.000s 19746.051us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 19746.051us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 23.000s 19746.051us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 28.000s 31996.460us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 4.000s 1429.929us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 17.000s 61379.339us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 3348.091us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 4816.073us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 4816.073us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 23.000s 19746.051us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 3.000s 1254.705us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 28.000s 31996.460us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 3.000s 1254.705us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1254.705us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 4816.073us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 3.000s 1254.705us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 16.000s 2359.050us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 64227068204253655044589229613046546095130940976162976453360241432199313365840 86
UVM_INFO @ 1320417777 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 46104353308569131716448026467922009816243947443493695624145010443410795494557 86
UVM_INFO @ 1991230675 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 68580916135816790036244064261379185885111893323927368928415862771727763670736 86
UVM_INFO @ 709054734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---