Simulation Results: sram_ctrl/ret

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 91.02 %
  • code
  • 81.85 %
  • assert
  • 97.26 %
  • func
  • 93.96 %
  • block
  • 93.08 %
  • line
  • 94.17 %
  • branch
  • 88.26 %
  • toggle
  • 78.31 %
  • FSM
  • 66.67 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 2.000s 77.438us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 90.071us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.492us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 1.000s 101.351us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.402us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 1.000s 117.123us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 52.492us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.402us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 8.000s 839.777us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 3.000s 116.525us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 9.000s 842.472us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 47.000s 2075.891us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 5.000s 559.658us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 13.000s 2646.463us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 5.000s 641.969us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 7.000s 678.177us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 2.000s 30.529us 1 1 100.00
sram_ctrl_partial_access_b2b 206.000s 33832.023us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 1.000s 69.671us 0 1 0.00
sram_ctrl_throughput_w_partial_write 2.000s 99.625us 0 1 0.00
sram_ctrl_throughput_w_readback 2.000s 144.782us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 8.000s 6234.817us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 1.000s 31.780us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 24.000s 2813.618us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 2.000s 30.091us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 515.762us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 3.000s 515.762us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 90.071us 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.492us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.402us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.331us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 90.071us 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.492us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 21.402us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 20.331us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 406.169us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 4.000s 5293.923us 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 445.684us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 4.000s 5293.923us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 1.000s 445.684us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 6234.817us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 8.000s 6234.817us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 52.492us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 7.000s 678.177us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 678.177us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 7.000s 678.177us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 5.000s 641.969us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 1.000s 163.278us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 2.000s 406.169us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 1.000s 400.560us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 77.438us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 2.000s 77.438us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 7.000s 678.177us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 4.000s 5293.923us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 5.000s 641.969us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 4.000s 5293.923us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 5293.923us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 2.000s 77.438us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 4.000s 5293.923us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 26.000s 804.109us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 101830534906560459551754221528969667158569342699868985958147737996783038317670 86
UVM_INFO @ 69671098 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 2267685399365818131828861000077249096161555227262987693255888011193142553251 86
UVM_INFO @ 99624985 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 76424074063160273979659060907052966822150601593631604198283671521198553423436 86
UVM_INFO @ 144781734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---