Simulation Results: sysrst_ctrl

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.45 %
  • code
  • 93.64 %
  • assert
  • 95.98 %
  • func
  • 60.73 %
  • line
  • 97.71 %
  • branch
  • 97.74 %
  • cond
  • 95.20 %
  • toggle
  • 100.00 %
  • FSM
  • 77.56 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 3.990s 2116.377us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.580s 2465.557us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.100s 2295.420us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 2.540s 2361.460us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 8.560s 4031.507us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.470s 2090.124us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 80.040s 76154.870us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 2.580s 3010.121us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 4.900s 2086.627us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.470s 2090.124us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.580s 3010.121us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 82.860s 50556.356us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 12.850s 26403.052us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 3.690s 3463.263us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 2.900s 3244.689us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.780s 2510.772us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 4.260s 2214.943us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 6.450s 3741.228us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.650s 2609.789us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 4.640s 3907.464us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 61.560s 36515.012us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 16.430s 11150.694us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 3.950s 2008.644us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 3.800s 2008.459us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 1.720s 2379.987us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 1.720s 2379.987us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.560s 4031.507us 1 1 100.00
sysrst_ctrl_csr_rw 1.470s 2090.124us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.580s 3010.121us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 22.260s 9675.638us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 8.560s 4031.507us 1 1 100.00
sysrst_ctrl_csr_rw 1.470s 2090.124us 1 1 100.00
sysrst_ctrl_csr_aliasing 2.580s 3010.121us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 22.260s 9675.638us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 30.290s 22015.283us 1 1 100.00
sysrst_ctrl_tl_intg_err 75.260s 42458.233us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 75.260s 42458.233us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 3.730s 26030.882us 1 1 100.00