Simulation Results: uart

 
07/07/2026 15:30:27 DVSim: v1.49.12 sha: 32d4560 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.35 %
  • code
  • 95.42 %
  • assert
  • 97.12 %
  • func
  • 48.52 %
  • line
  • 98.86 %
  • branch
  • 96.74 %
  • cond
  • 94.52 %
  • toggle
  • 91.55 %
Validation stages
V1
100.00%
V2
95.45%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 14.810s 5496.209us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.710s 15.815us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.570s 13.210us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.670s 288.297us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.840s 21.340us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.750s 45.538us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.570s 13.210us 1 1 100.00
uart_csr_aliasing 0.840s 21.340us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 43.770s 41713.663us 1 1 100.00
parity 2 2 100.00
uart_smoke 14.810s 5496.209us 1 1 100.00
uart_tx_rx 43.770s 41713.663us 1 1 100.00
parity_error 2 2 100.00
uart_intr 1.340s 4251.301us 1 1 100.00
uart_rx_parity_err 18.580s 47875.862us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 43.770s 41713.663us 1 1 100.00
uart_intr 1.340s 4251.301us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 5.880s 19046.336us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 69.420s 29942.347us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 38.500s 43759.542us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 1.340s 4251.301us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 1.340s 4251.301us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 1.340s 4251.301us 1 1 100.00
perf 1 1 100.00
uart_perf 90.830s 15071.680us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 6.160s 9278.814us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 6.160s 9278.814us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 30.450s 70489.459us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 5.830s 4912.050us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.330s 878.427us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 7.020s 7494.472us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 125.020s 77037.490us 1 1 100.00
stress_all 0 1 0.00
uart_stress_all 32.130s 87410.656us 0 1 0.00
alert_test 1 1 100.00
uart_alert_test 0.620s 40.589us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.570s 13.297us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.200s 115.647us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.200s 115.647us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.710s 15.815us 1 1 100.00
uart_csr_rw 0.570s 13.210us 1 1 100.00
uart_csr_aliasing 0.840s 21.340us 1 1 100.00
uart_same_csr_outstanding 0.930s 61.848us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.710s 15.815us 1 1 100.00
uart_csr_rw 0.570s 13.210us 1 1 100.00
uart_csr_aliasing 0.840s 21.340us 1 1 100.00
uart_same_csr_outstanding 0.930s 61.848us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.820s 148.005us 1 1 100.00
uart_tl_intg_err 1.540s 102.256us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 1.540s 102.256us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 51.980s 3678.538us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (uart_scoreboard.sv:377) [scoreboard] Check failed get_field_val(ral.status.rxempty, item.d_data) == rx_empty_exp (* [*] vs * [*]) check rx_empty fail: uart_rx_clk_pulses = *, rx_q.size = * 1 test run
uart_stress_all 3461099455818879080015630563411778015013250796588153941741805923127661890070 89
UVM_ERROR @ 85153689605 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
UVM_ERROR @ 85153689605 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
UVM_ERROR @ 85184260575 ps: (uart_scoreboard.sv:501) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] rxlvl mismatch exp: 0 (+/-1), act: 6, clk_pulses: 3
UVM_ERROR @ 85184317717 ps: (uart_scoreboard.sv:462) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] unexpected read when fifo is empty