Simulation Results

Simulation Results: adc_ctrl

08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
65.96 %

code
92.68 %

assert
92.06 %

func
13.14 %

line
97.97 %

branch
96.23 %

cond
85.65 %

toggle
99.76 %

FSM
83.78 %

Validation stages

V1		100.00%
V2		52.63%
V2S		100.00%
V3		100.00%

6/6 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
smoke				1	1	100.00
	adc_ctrl_smoke	2.100s	5792.629us	1	1	100.00
csr_hw_reset				1	1	100.00
	adc_ctrl_csr_hw_reset	2.340s	1300.878us	1	1	100.00
csr_rw				1	1	100.00
	adc_ctrl_csr_rw	0.690s	456.094us	1	1	100.00
csr_bit_bash				1	1	100.00
	adc_ctrl_csr_bit_bash	28.620s	49944.487us	1	1	100.00
csr_aliasing				1	1	100.00
	adc_ctrl_csr_aliasing	2.380s	796.407us	1	1	100.00
csr_mem_rw_with_rand_reset				1	1	100.00
	adc_ctrl_csr_mem_rw_with_rand_reset	0.990s	392.678us	1	1	100.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	adc_ctrl_csr_rw	0.690s	456.094us	1	1	100.00
	adc_ctrl_csr_aliasing	2.380s	796.407us	1	1	100.00

10/19 passed

52.63 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
filters_polled				0	1	0.00
	adc_ctrl_filters_polled	0.860s	398.146us	0	1	0.00
filters_polled_fixed				0	1	0.00
	adc_ctrl_filters_polled_fixed	1.310s	420.059us	0	1	0.00
filters_interrupt				0	1	0.00
	adc_ctrl_filters_interrupt	0.640s	332.929us	0	1	0.00
filters_interrupt_fixed				0	1	0.00
	adc_ctrl_filters_interrupt_fixed	0.840s	510.822us	0	1	0.00
filters_wakeup				0	1	0.00
	adc_ctrl_filters_wakeup	0.810s	433.890us	0	1	0.00
filters_wakeup_fixed				0	1	0.00
	adc_ctrl_filters_wakeup_fixed	1.070s	333.412us	0	1	0.00
filters_both				0	1	0.00
	adc_ctrl_filters_both	1.090s	406.428us	0	1	0.00
clock_gating				0	1	0.00
	adc_ctrl_clock_gating	0.680s	487.008us	0	1	0.00
poweron_counter				1	1	100.00
	adc_ctrl_poweron_counter	1.080s	3879.150us	1	1	100.00
lowpower_counter				1	1	100.00
	adc_ctrl_lowpower_counter	9.380s	24441.224us	1	1	100.00
fsm_reset				1	1	100.00
	adc_ctrl_fsm_reset	44.560s	123656.023us	1	1	100.00
stress_all				0	1	0.00
	adc_ctrl_stress_all	0.750s	831.894us	0	1	0.00
alert_test				1	1	100.00
	adc_ctrl_alert_test	0.650s	572.495us	1	1	100.00
intr_test				1	1	100.00
	adc_ctrl_intr_test	0.640s	522.398us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	adc_ctrl_tl_errors	1.450s	363.624us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	adc_ctrl_tl_errors	1.450s	363.624us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	adc_ctrl_csr_hw_reset	2.340s	1300.878us	1	1	100.00
	adc_ctrl_csr_rw	0.690s	456.094us	1	1	100.00
	adc_ctrl_csr_aliasing	2.380s	796.407us	1	1	100.00
	adc_ctrl_same_csr_outstanding	4.050s	4737.005us	1	1	100.00
tl_d_partial_access				4	4	100.00
	adc_ctrl_csr_hw_reset	2.340s	1300.878us	1	1	100.00
	adc_ctrl_csr_rw	0.690s	456.094us	1	1	100.00
	adc_ctrl_csr_aliasing	2.380s	796.407us	1	1	100.00
	adc_ctrl_same_csr_outstanding	4.050s	4737.005us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
tl_intg_err				2	2	100.00
	adc_ctrl_sec_cm	2.120s	4331.487us	1	1	100.00
	adc_ctrl_tl_intg_err	4.190s	8203.862us	1	1	100.00
sec_cm_bus_integrity				1	1	100.00
	adc_ctrl_tl_intg_err	4.190s	8203.862us	1	1	100.00

1/1 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
stress_all_with_rand_reset				1	1	100.00
	adc_ctrl_stress_all_with_rand_reset	5.730s	2504.272us	1	1	100.00

Error Messages

	Test	seed	line	log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [, ]				9 test runs
	adc_ctrl_filters_polled	93254095413832983823448762119994122839540914227955561100758261045069669088450	386	UVM_INFO @ 398145624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_polled_fixed	57863275345349095684175883957646460855960984502019936489889359148277702723775	386	UVM_INFO @ 420058824 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt	54037656351901480419783862374362056667008121660638924556818573217358332055883	386	UVM_INFO @ 332929396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_interrupt_fixed	79514767949787948398895511076654192716567793923922590002462938623430797799393	386	UVM_INFO @ 510821946 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup	879518798635293594743743520610376320176513698336044557468784760855570802642	386	UVM_INFO @ 433890015 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_wakeup_fixed	106391787470900772184108500751479051074420009300514648084780289718693677949279	386	UVM_INFO @ 333412153 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_clock_gating	111753022293394935326064473656064940503505131237793758116032545447420298290469	386	UVM_INFO @ 487008489 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_filters_both	111265737749805774711995880755810789669413107573988499577667656845629818060562	386	UVM_INFO @ 406428003 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	adc_ctrl_stress_all	82647945986977355111491019380040632727331623939587118253764055924656135964293	387	UVM_INFO @ 831893843 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---