Simulation Results: aes/masked

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.54 %
  • code
  • 93.59 %
  • assert
  • 98.23 %
  • func
  • 73.80 %
  • block
  • 94.25 %
  • line
  • 95.91 %
  • branch
  • 87.14 %
  • toggle
  • 97.99 %
  • FSM
  • 93.33 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 6.000s 459.446us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 95.555us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 52.269us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 82.711us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 9.000s 3130.372us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 178.097us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 55.223us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 82.711us 1 1 100.00
aes_csr_aliasing 2.000s 178.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 95.555us 1 1 100.00
aes_config_error 3.000s 306.957us 1 1 100.00
aes_stress 3.000s 75.902us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 95.555us 1 1 100.00
aes_config_error 3.000s 306.957us 1 1 100.00
aes_stress 3.000s 75.902us 1 1 100.00
back2back 2 2 100.00
aes_stress 3.000s 75.902us 1 1 100.00
aes_b2b 3.000s 79.760us 1 1 100.00
backpressure 1 1 100.00
aes_stress 3.000s 75.902us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 95.555us 1 1 100.00
aes_config_error 3.000s 306.957us 1 1 100.00
aes_stress 3.000s 75.902us 1 1 100.00
aes_alert_reset 6.000s 465.115us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 85.567us 1 1 100.00
aes_config_error 3.000s 306.957us 1 1 100.00
aes_alert_reset 6.000s 465.115us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 3.000s 244.451us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 7.000s 4341.550us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 6.000s 465.115us 1 1 100.00
stress 1 1 100.00
aes_stress 3.000s 75.902us 1 1 100.00
sideload 2 2 100.00
aes_stress 3.000s 75.902us 1 1 100.00
aes_sideload 3.000s 140.443us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 245.202us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 8.000s 128.391us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 58.159us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 328.206us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 328.206us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 52.269us 1 1 100.00
aes_csr_rw 1.000s 82.711us 1 1 100.00
aes_csr_aliasing 2.000s 178.097us 1 1 100.00
aes_same_csr_outstanding 2.000s 72.173us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 52.269us 1 1 100.00
aes_csr_rw 1.000s 82.711us 1 1 100.00
aes_csr_aliasing 2.000s 178.097us 1 1 100.00
aes_same_csr_outstanding 2.000s 72.173us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 4.000s 93.142us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 4.000s 1331.244us 0 1 0.00
aes_control_fi 1.000s 54.402us 1 1 100.00
aes_cipher_fi 3.000s 51.360us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 413.830us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 413.830us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 413.830us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 413.830us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 413.597us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 4.000s 1523.207us 1 1 100.00
aes_tl_intg_err 2.000s 623.574us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 623.574us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 6.000s 465.115us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 413.830us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 413.830us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 95.555us 1 1 100.00
aes_stress 3.000s 75.902us 1 1 100.00
aes_alert_reset 6.000s 465.115us 1 1 100.00
aes_core_fi 2.000s 93.928us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 3.000s 306.957us 1 1 100.00
aes_stress 3.000s 75.902us 1 1 100.00
aes_core_fi 2.000s 93.928us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 413.830us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 88.370us 1 1 100.00
aes_stress 3.000s 75.902us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 3.000s 75.902us 1 1 100.00
aes_sideload 3.000s 140.443us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 88.370us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 88.370us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 88.370us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 88.370us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 88.370us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 3.000s 75.902us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 3.000s 75.902us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 4.000s 1331.244us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 4.000s 1331.244us 0 1 0.00
aes_control_fi 1.000s 54.402us 1 1 100.00
aes_cipher_fi 3.000s 51.360us 1 1 100.00
aes_ctr_fi 2.000s 81.411us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 4.000s 1331.244us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 4.000s 1331.244us 0 1 0.00
aes_control_fi 1.000s 54.402us 1 1 100.00
aes_cipher_fi 3.000s 51.360us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 3.000s 51.360us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 4.000s 1331.244us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 4.000s 1331.244us 0 1 0.00
aes_control_fi 1.000s 54.402us 1 1 100.00
aes_ctr_fi 2.000s 81.411us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 4.000s 1331.244us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 4.000s 1331.244us 0 1 0.00
aes_control_fi 1.000s 54.402us 1 1 100.00
aes_cipher_fi 3.000s 51.360us 1 1 100.00
aes_ctr_fi 2.000s 81.411us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 6.000s 465.115us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 4.000s 1331.244us 0 1 0.00
aes_control_fi 1.000s 54.402us 1 1 100.00
aes_cipher_fi 3.000s 51.360us 1 1 100.00
aes_ctr_fi 2.000s 81.411us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 4.000s 1331.244us 0 1 0.00
aes_control_fi 1.000s 54.402us 1 1 100.00
aes_cipher_fi 3.000s 51.360us 1 1 100.00
aes_ctr_fi 2.000s 81.411us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 4.000s 1331.244us 0 1 0.00
aes_control_fi 1.000s 54.402us 1 1 100.00
aes_ctr_fi 2.000s 81.411us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 4.000s 1331.244us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 4.000s 1331.244us 0 1 0.00
aes_control_fi 1.000s 54.402us 1 1 100.00
aes_cipher_fi 3.000s 51.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 3.000s 87.850us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 3 test runs
aes_reseed 21483157949417335420450535138926601501292895319603368739669534495477235187418 15004
UVM_INFO @ 93142004 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all 3245257542069586625186345385341075690549737084958006840331864103263048652812 9421
UVM_INFO @ 128390605 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
aes_stress_all_with_rand_reset 56192524329405705222870996485700266505539505958635045340305038649027966118483 186
UVM_INFO @ 87849961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 43747916945224332511766782019836320336837772953600624678049439660159752726223 6569
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 3
----| Seen: 2
----| Expected corrupted: 0