Simulation Results: aes/unmasked

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.27 %
  • code
  • 89.50 %
  • assert
  • 97.73 %
  • func
  • 74.57 %
  • block
  • 89.32 %
  • line
  • 91.65 %
  • branch
  • 79.46 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
94.12%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 66.952us 1 1 100.00
smoke 1 1 100.00
aes_smoke 2.000s 80.939us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 272.722us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 1.000s 66.341us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 4.000s 452.809us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 2.000s 190.219us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 1.000s 63.339us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 1.000s 66.341us 1 1 100.00
aes_csr_aliasing 2.000s 190.219us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 2.000s 80.939us 1 1 100.00
aes_config_error 2.000s 182.793us 1 1 100.00
aes_stress 2.000s 62.534us 1 1 100.00
key_length 3 3 100.00
aes_smoke 2.000s 80.939us 1 1 100.00
aes_config_error 2.000s 182.793us 1 1 100.00
aes_stress 2.000s 62.534us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 62.534us 1 1 100.00
aes_b2b 2.000s 227.507us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 62.534us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 2.000s 80.939us 1 1 100.00
aes_config_error 2.000s 182.793us 1 1 100.00
aes_stress 2.000s 62.534us 1 1 100.00
aes_alert_reset 2.000s 76.293us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 2.000s 137.832us 1 1 100.00
aes_config_error 2.000s 182.793us 1 1 100.00
aes_alert_reset 2.000s 76.293us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 69.585us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 4.000s 224.085us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 76.293us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 62.534us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 62.534us 1 1 100.00
aes_sideload 3.000s 301.774us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 2.000s 76.351us 1 1 100.00
stress_all 0 1 0.00
aes_stress_all 9.000s 232.533us 0 1 0.00
alert_test 1 1 100.00
aes_alert_test 2.000s 55.592us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 1.000s 258.556us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 1.000s 258.556us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 272.722us 1 1 100.00
aes_csr_rw 1.000s 66.341us 1 1 100.00
aes_csr_aliasing 2.000s 190.219us 1 1 100.00
aes_same_csr_outstanding 2.000s 72.038us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 272.722us 1 1 100.00
aes_csr_rw 1.000s 66.341us 1 1 100.00
aes_csr_aliasing 2.000s 190.219us 1 1 100.00
aes_same_csr_outstanding 2.000s 72.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 1 1 100.00
aes_reseed 2.000s 102.508us 1 1 100.00
fault_inject 1 3 33.33
aes_fi 3.000s 338.021us 0 1 0.00
aes_control_fi 2.000s 46.969us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 2.000s 136.282us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 2.000s 136.282us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 2.000s 136.282us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 2.000s 136.282us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 3.000s 441.451us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 3.000s 1929.796us 1 1 100.00
aes_tl_intg_err 2.000s 1845.281us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 1845.281us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 76.293us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 136.282us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 136.282us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 2.000s 80.939us 1 1 100.00
aes_stress 2.000s 62.534us 1 1 100.00
aes_alert_reset 2.000s 76.293us 1 1 100.00
aes_core_fi 2.000s 102.304us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 182.793us 1 1 100.00
aes_stress 2.000s 62.534us 1 1 100.00
aes_core_fi 2.000s 102.304us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 2.000s 136.282us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 1.000s 60.782us 1 1 100.00
aes_stress 2.000s 62.534us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 62.534us 1 1 100.00
aes_sideload 3.000s 301.774us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 1.000s 60.782us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 1.000s 60.782us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 1.000s 60.782us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 1.000s 60.782us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 1.000s 60.782us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 62.534us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 62.534us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 3.000s 338.021us 0 1 0.00
sec_cm_main_fsm_redun 2 4 50.00
aes_fi 3.000s 338.021us 0 1 0.00
aes_control_fi 2.000s 46.969us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 79.508us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 3.000s 338.021us 0 1 0.00
sec_cm_cipher_fsm_redun 1 3 33.33
aes_fi 3.000s 338.021us 0 1 0.00
aes_control_fi 2.000s 46.969us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
sec_cm_cipher_ctr_redun 0 1 0.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 3.000s 338.021us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 3.000s 338.021us 0 1 0.00
aes_control_fi 2.000s 46.969us 1 1 100.00
aes_ctr_fi 2.000s 79.508us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 3.000s 338.021us 0 1 0.00
sec_cm_ctrl_sparse 2 4 50.00
aes_fi 3.000s 338.021us 0 1 0.00
aes_control_fi 2.000s 46.969us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 79.508us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 76.293us 1 1 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
aes_fi 3.000s 338.021us 0 1 0.00
aes_control_fi 2.000s 46.969us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 79.508us 1 1 100.00
sec_cm_cipher_fsm_local_esc 2 4 50.00
aes_fi 3.000s 338.021us 0 1 0.00
aes_control_fi 2.000s 46.969us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
aes_ctr_fi 2.000s 79.508us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 3.000s 338.021us 0 1 0.00
aes_control_fi 2.000s 46.969us 1 1 100.00
aes_ctr_fi 2.000s 79.508us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 3.000s 338.021us 0 1 0.00
sec_cm_data_reg_local_esc 1 3 33.33
aes_fi 3.000s 338.021us 0 1 0.00
aes_control_fi 2.000s 46.969us 1 1 100.00
aes_cipher_fi 60.000s 0.000us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 6.259us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 49314092357700293173376155634414744111970864819620439856848297496985661732226 5352
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 2
----| Expected corrupted: 0
Job timed out after * minutes 1 test run
aes_cipher_fi 86327847205701928808910920129806760715949040090473113721008263631642547826244 None
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_stress_all 80321548271063864462730696521631414205558565406246371235585504732314215758291 9912
UVM_INFO @ 232532717 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 110914080842647560705693946665769596614104998392795613345147128057183063788628 135
UVM_INFO @ 6259462 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---