Simulation Results: alert_handler

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.59 %
  • code
  • 92.23 %
  • assert
  • 98.02 %
  • func
  • 81.52 %
  • line
  • 99.76 %
  • branch
  • 98.33 %
  • cond
  • 91.89 %
  • toggle
  • 88.90 %
  • FSM
  • 82.26 %
Validation stages
V1
100.00%
V2
94.74%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 34.160s 3570.926us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.080s 126.420us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 5.370s 114.054us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 313.270s 17652.383us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 35.750s 561.136us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 4.220s 92.576us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 5.370s 114.054us 1 1 100.00
alert_handler_csr_aliasing 35.750s 561.136us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 26.870s 2119.169us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 37.420s 9895.540us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 952.120s 123382.763us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 6.830s 96.151us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 34.160s 3570.926us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 25.590s 1137.668us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 21.910s 693.597us 1 1 100.00
ping_timeout 1 1 100.00
alert_handler_ping_timeout 64.180s 5244.539us 1 1 100.00
lpg 2 2 100.00
alert_handler_lpg 2173.210s 65569.025us 1 1 100.00
alert_handler_lpg_stub_clk 1154.590s 39218.119us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1243.010s 67501.960us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 3.870s 164.329us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 2.120s 19.127us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.130s 16.299us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 15.000s 2100.913us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 15.000s 2100.913us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.080s 126.420us 1 1 100.00
alert_handler_csr_rw 5.370s 114.054us 1 1 100.00
alert_handler_csr_aliasing 35.750s 561.136us 1 1 100.00
alert_handler_same_csr_outstanding 12.220s 172.654us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.080s 126.420us 1 1 100.00
alert_handler_csr_rw 5.370s 114.054us 1 1 100.00
alert_handler_csr_aliasing 35.750s 561.136us 1 1 100.00
alert_handler_same_csr_outstanding 12.220s 172.654us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 213.080s 10041.402us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 213.080s 10041.402us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 213.080s 10041.402us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 213.080s 10041.402us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 171.540s 41885.283us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 30.810s 1099.948us 1 1 100.00
alert_handler_tl_intg_err 2.170s 110.495us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 2.170s 110.495us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 213.080s 10041.402us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 34.160s 3570.926us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 34.160s 3570.926us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 34.160s 3570.926us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 34.160s 3570.926us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 6.830s 96.151us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2173.210s 65569.025us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 6.830s 96.151us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 952.120s 123382.763us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 952.120s 123382.763us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 30.810s 1099.948us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 30.810s 1099.948us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 30.810s 1099.948us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 30.810s 1099.948us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 30.810s 1099.948us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 30.810s 1099.948us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 30.810s 1099.948us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 30.810s 1099.948us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 30.810s 1099.948us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 12.380s 275.407us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 40508056794626430520607398139937992789161114875732415513083755808765418585322 120
UVM_INFO @ 164329290 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 97526078564477343796295338631074316242836804266860144123214545018391929232862 86
UVM_INFO @ 275406976 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---