Simulation Results

Simulation Results: chip

08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
71.41 %

code
84.45 %

assert
97.49 %

func
32.29 %

line
94.28 %

branch
93.70 %

cond
89.97 %

toggle
87.17 %

FSM
57.14 %

Validation stages

V1		94.44%
V2		75.81%
V2S		100.00%
V3		65.38%
unmapped		63.64%

17/18 passed

94.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	147.060s	2908.960us	1	1	100.00
	chip_sw_example_rom	62.870s	1974.301us	1	1	100.00
	chip_sw_example_manufacturer	156.030s	2583.285us	1	1	100.00
	chip_sw_example_concurrency	160.130s	3033.074us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	155.620s	4447.007us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	211.510s	3983.804us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	499.370s	6730.382us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	3914.170s	28259.433us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	chip_csr_mem_rw_with_rand_reset	75.080s	2405.929us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	3914.170s	28259.433us	1	1	100.00
	chip_csr_rw	211.510s	3983.804us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	6.070s	218.662us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	305.480s	4436.449us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	305.480s	4436.449us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	305.480s	4436.449us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	334.880s	4358.997us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	334.880s	4358.997us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	291.380s	4177.783us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	304.370s	4638.711us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	356.100s	4218.358us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	343.900s	4053.367us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	936.750s	7597.506us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	648.000s	8416.674us	1	1	100.00

210/277 passed

75.81 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	203.740s	4927.721us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	203.740s	4927.721us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				1	1	100.00
	chip_sw_sleep_pin_mio_dio_val	156.700s	3809.164us	1	1	100.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	335.380s	6632.885us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	204.920s	4100.729us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	104.690s	3157.922us	1	1	100.00
	chip_tap_straps_testunlock0	502.570s	9154.711us	1	1	100.00
	chip_tap_straps_rma	125.410s	2944.001us	1	1	100.00
	chip_tap_straps_prod	77.730s	2476.965us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	442.680s	5874.422us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	442.680s	5874.422us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	534.750s	7473.792us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	893.360s	10019.600us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	330.760s	4596.299us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	495.540s	6035.800us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3780.980s	18866.733us	1	1	100.00
	chip_sw_aes_enc_jitter_en	139.850s	2495.854us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	742.460s	6252.323us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	112.900s	2976.511us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1152.820s	10867.078us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	142.830s	2822.353us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	275.740s	4212.251us	1	1	100.00
	chip_sw_clkmgr_jitter	177.080s	2698.767us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	182.150s	3414.660us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	225.860s	4682.846us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	249.220s	5348.670us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	139.400s	3135.703us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	249.220s	5348.670us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	122.960s	2643.016us	1	1	100.00
	chip_sw_aes_smoketest	141.180s	2453.131us	1	1	100.00
	chip_sw_aon_timer_smoketest	209.690s	3090.157us	1	1	100.00
	chip_sw_clkmgr_smoketest	132.250s	3182.030us	1	1	100.00
	chip_sw_csrng_smoketest	159.870s	3575.515us	1	1	100.00
	chip_sw_entropy_src_smoketest	748.150s	6913.047us	1	1	100.00
	chip_sw_gpio_smoketest	135.890s	3074.278us	1	1	100.00
	chip_sw_hmac_smoketest	179.410s	3029.495us	1	1	100.00
	chip_sw_kmac_smoketest	146.000s	3501.139us	1	1	100.00
	chip_sw_otbn_smoketest	833.210s	7566.159us	1	1	100.00
	chip_sw_pwrmgr_smoketest	260.670s	6160.194us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	304.170s	6748.140us	1	1	100.00
	chip_sw_rv_plic_smoketest	129.530s	2868.090us	1	1	100.00
	chip_sw_rv_timer_smoketest	117.790s	2652.058us	1	1	100.00
	chip_sw_rstmgr_smoketest	136.900s	3422.790us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	123.890s	2904.710us	1	1	100.00
	chip_sw_uart_smoketest	162.490s	3172.614us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	164.850s	3488.679us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	296.490s	4530.157us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7930.670s	61238.135us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3018.800s	14701.714us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	20.686s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	960.370s	14368.463us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	616.700s	14845.221us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	6638.470s	51330.736us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7250.350s	54707.403us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	150.730s	3635.514us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	150.730s	3635.514us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	3914.170s	28259.433us	1	1	100.00
	chip_same_csr_outstanding	1244.250s	14036.722us	1	1	100.00
	chip_csr_hw_reset	155.620s	4447.007us	1	1	100.00
	chip_csr_rw	211.510s	3983.804us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	3914.170s	28259.433us	1	1	100.00
	chip_same_csr_outstanding	1244.250s	14036.722us	1	1	100.00
	chip_csr_hw_reset	155.620s	4447.007us	1	1	100.00
	chip_csr_rw	211.510s	3983.804us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	15.140s	204.061us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.160s	50.475us	1	1	100.00
	xbar_smoke_large_delays	22.090s	4149.155us	1	1	100.00
	xbar_smoke_slow_rsp	31.870s	4091.276us	1	1	100.00
	xbar_random_zero_delays	12.720s	199.927us	1	1	100.00
	xbar_random_large_delays	143.410s	26196.851us	1	1	100.00
	xbar_random_slow_rsp	20.760s	2507.397us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	11.870s	159.524us	1	1	100.00
	xbar_error_and_unmapped_addr	35.600s	1363.619us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	8.400s	328.893us	1	1	100.00
	xbar_error_and_unmapped_addr	35.600s	1363.619us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	10.440s	332.001us	1	1	100.00
	xbar_access_same_device_slow_rsp	239.970s	31423.252us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	31.630s	1625.533us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	41.310s	966.092us	1	1	100.00
	xbar_stress_all_with_error	315.270s	16085.667us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	32.760s	166.909us	1	1	100.00
	xbar_stress_all_with_reset_error	38.390s	251.010us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3018.800s	14701.714us	1	1	100.00
rom_e2e_shutdown_output				0	1	0.00
	rom_e2e_shutdown_output	526.940s	11625.751us	0	1	0.00
rom_e2e_shutdown_exception_c				0	1	0.00
	rom_e2e_shutdown_exception_c	414.130s	5694.175us	0	1	0.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	51.918s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	14.657s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	32.117s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	18.087s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	12.200s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	121.203s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	15.197s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	16.297s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	8.467s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	15.162s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	127.760s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	37.074s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	47.475s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	25.298s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	18.029s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	19.480s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	19.680s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	18.560s	10.240us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	18.250s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	24.150s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	18.560s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	19.230s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.820s	10.160us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.330s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	19.240s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	21.600s	10.380us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	20.780s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	20.140s	10.340us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	19.450s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.180s	10.120us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	130.822s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	73.514s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	79.057s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	27.841s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	10.230s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	3220.160s	16499.322us	0	1	0.00
	rom_e2e_keymgr_init_rom_ext_no_meas	5740.810s	28965.598us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	5878.810s	27608.704us	1	1	100.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3185.510s	16652.566us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2967.180s	34602.798us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2967.180s	34602.798us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	238.040s	3589.134us	1	1	100.00
	chip_sw_aes_enc_jitter_en	139.850s	2495.854us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	185.670s	2564.527us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	109.120s	2475.412us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1307.970s	11433.316us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	152.860s	2791.354us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	286.190s	5631.757us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	413.810s	5732.165us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	451.360s	4515.980us	1	1	100.00
	chip_plic_all_irqs_10	282.780s	3679.725us	1	1	100.00
	chip_plic_all_irqs_20	345.680s	4375.101us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	199.740s	4080.483us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	1145.750s	14677.512us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	360.370s	5060.875us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	149.090s	3324.096us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.173s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	647.960s	5629.092us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1264.010s	8812.988us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	809.810s	8218.472us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	7869.560s	254812.302us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	229.410s	4504.246us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	260.670s	6160.194us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	229.410s	4504.246us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	348.450s	8073.516us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_bite_reset				0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	348.450s	8073.516us	0	1	0.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	253.480s	6756.053us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	319.640s	5970.627us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	509.260s	6005.920us	1	1	100.00
	chip_sw_aes_idle	109.120s	2475.412us	1	1	100.00
	chip_sw_hmac_enc_idle	182.680s	3237.559us	1	1	100.00
	chip_sw_kmac_idle	152.190s	3515.416us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	230.220s	4028.102us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	284.230s	4354.539us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	283.060s	5295.588us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	311.420s	5723.915us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	754.630s	11613.585us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	389.430s	4525.245us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	410.200s	5365.415us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	369.820s	4447.162us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	367.550s	4656.917us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	357.210s	3870.172us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	369.860s	5043.671us	1	1	100.00
	chip_sw_ast_clk_outputs	534.750s	7473.792us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				0	1	0.00
	chip_sw_clkmgr_external_clk_src_for_lc	936.040s	25864.258us	0	1	0.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	369.820s	4447.162us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	367.550s	4656.917us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	330.760s	4596.299us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	495.540s	6035.800us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3780.980s	18866.733us	1	1	100.00
	chip_sw_aes_enc_jitter_en	139.850s	2495.854us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	742.460s	6252.323us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	112.900s	2976.511us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1152.820s	10867.078us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	142.830s	2822.353us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	275.740s	4212.251us	1	1	100.00
	chip_sw_clkmgr_jitter	177.080s	2698.767us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	111.560s	2468.912us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	365.650s	4407.805us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	526.650s	6754.632us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4030.370s	25270.556us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	134.360s	2969.994us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	127.120s	3407.946us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	1038.350s	13413.558us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	156.000s	2895.371us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	309.470s	4847.003us	1	1	100.00
	chip_sw_flash_init_reduced_freq	987.170s	24350.449us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	3268.390s	23278.724us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	534.750s	7473.792us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	352.670s	4837.472us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	286.780s	3064.120us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	413.810s	5732.165us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	647.960s	5629.092us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	759.530s	6024.418us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	266.420s	4712.264us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	474.510s	7809.117us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	172.840s	2973.496us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	4947.200s	27303.270us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	140.490s	3102.629us	1	1	100.00
	chip_sw_edn_entropy_reqs	624.400s	6601.504us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	140.490s	3102.629us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	759.530s	6024.418us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	131.830s	3342.252us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	935.560s	21410.257us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	483.340s	5562.010us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	495.540s	6035.800us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	343.200s	4215.260us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	330.760s	4596.299us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3354.220s	42745.611us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	935.560s	21410.257us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	225.150s	3666.644us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	608.030s	7447.522us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	156.040s	3319.280us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3354.220s	42745.611us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	156.040s	3319.280us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	156.040s	3319.280us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	156.040s	3319.280us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	156.040s	3319.280us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	413.810s	5732.165us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	193.560s	6378.460us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	535.850s	5656.429us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	325.020s	4897.082us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	325.020s	4897.082us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	140.380s	3207.818us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	112.900s	2976.511us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	182.680s	3237.559us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	1328.190s	11655.094us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1490.490s	12018.655us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	338.980s	4741.405us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	284.920s	4920.637us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	252.510s	4892.448us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	240.940s	4011.954us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	608.030s	7447.522us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1152.820s	10867.078us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	640.270s	8136.062us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1307.970s	11433.316us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4587.780s	20026.891us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	135.070s	3265.475us	1	1	100.00
	chip_sw_kmac_mode_kmac	193.850s	3308.785us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	142.830s	2822.353us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	608.030s	7447.522us	1	1	100.00
chip_sw_kmac_app_lc				0	1	0.00
	chip_sw_lc_ctrl_transition	817.850s	25832.175us	0	1	0.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	128.950s	3062.784us	1	1	100.00
chip_sw_kmac_entropy				1	1	100.00
	chip_sw_kmac_entropy	1306.330s	10134.336us	1	1	100.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	152.190s	3515.416us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	286.190s	5631.757us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	104.690s	3157.922us	1	1	100.00
	chip_tap_straps_rma	125.410s	2944.001us	1	1	100.00
	chip_tap_straps_prod	77.730s	2476.965us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	147.450s	2872.432us	1	1	100.00
chip_sw_lc_ctrl_init				0	1	0.00
	chip_sw_lc_ctrl_transition	817.850s	25832.175us	0	1	0.00
chip_sw_lc_ctrl_transitions				0	1	0.00
	chip_sw_lc_ctrl_transition	817.850s	25832.175us	0	1	0.00
chip_sw_lc_ctrl_kmac_req				0	1	0.00
	chip_sw_lc_ctrl_transition	817.850s	25832.175us	0	1	0.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1323.340s	11978.343us	1	1	100.00
chip_sw_lc_ctrl_broadcast				17	22	77.27
	chip_sw_flash_ctrl_lc_rw_en	156.040s	3319.280us	0	1	0.00
	chip_sw_flash_rma_unlocked	3354.220s	42745.611us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	167.240s	3159.389us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	409.970s	5770.614us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	453.200s	6518.405us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	425.580s	6961.859us	0	1	0.00
	chip_sw_lc_ctrl_transition	817.850s	25832.175us	0	1	0.00
	chip_sw_keymgr_key_derivation	608.030s	7447.522us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	341.700s	10190.310us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	320.410s	6139.902us	1	1	100.00
	chip_prim_tl_access	193.560s	6378.460us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	936.040s	25864.258us	0	1	0.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	389.430s	4525.245us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	410.200s	5365.415us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	369.820s	4447.162us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	367.550s	4656.917us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	357.210s	3870.172us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	369.860s	5043.671us	1	1	100.00
	chip_tap_straps_dev	104.690s	3157.922us	1	1	100.00
	chip_tap_straps_rma	125.410s	2944.001us	1	1	100.00
	chip_tap_straps_prod	77.730s	2476.965us	1	1	100.00
	chip_rv_dm_lc_disabled	189.440s	5961.398us	0	1	0.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	132.700s	3911.930us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	82.740s	3105.860us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	90.180s	3901.517us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	81.450s	3019.931us	1	1	100.00
chip_lc_test_locked				1	2	50.00
	chip_sw_lc_walkthrough_testunlocks	1454.980s	34630.230us	1	1	100.00
	chip_rv_dm_lc_disabled	189.440s	5961.398us	0	1	0.00
chip_sw_lc_walkthrough				2	5	40.00
	chip_sw_lc_walkthrough_dev	604.730s	10084.785us	0	1	0.00
	chip_sw_lc_walkthrough_prod	675.570s	10823.073us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	445.400s	9117.959us	1	1	100.00
	chip_sw_lc_walkthrough_rma	295.440s	5748.754us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1454.980s	34630.230us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	77.640s	2477.993us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	71.330s	2719.023us	1	1	100.00
	rom_volatile_raw_unlock	123.534s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3756.430s	17006.628us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3780.980s	18866.733us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	509.260s	6005.920us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	509.260s	6005.920us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	509.260s	6005.920us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	262.680s	3912.029us	1	1	100.00
chip_otp_ctrl_init				0	1	0.00
	chip_sw_lc_ctrl_transition	817.850s	25832.175us	0	1	0.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	935.560s	21410.257us	1	1	100.00
	chip_sw_otbn_mem_scramble	262.680s	3912.029us	1	1	100.00
	chip_sw_keymgr_key_derivation	608.030s	7447.522us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	297.930s	4982.918us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	149.220s	3079.010us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	935.560s	21410.257us	1	1	100.00
	chip_sw_otbn_mem_scramble	262.680s	3912.029us	1	1	100.00
	chip_sw_keymgr_key_derivation	608.030s	7447.522us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	297.930s	4982.918us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	149.220s	3079.010us	1	1	100.00
chip_sw_otp_ctrl_program				0	1	0.00
	chip_sw_lc_ctrl_transition	817.850s	25832.175us	0	1	0.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	255.700s	5297.314us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	147.450s	2872.432us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				4	6	66.67
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	167.240s	3159.389us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	409.970s	5770.614us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	453.200s	6518.405us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	425.580s	6961.859us	0	1	0.00
	chip_sw_lc_ctrl_transition	817.850s	25832.175us	0	1	0.00
	chip_prim_tl_access	193.560s	6378.460us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	193.560s	6378.460us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	821.140s	6975.321us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	66.110s	2346.880us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	794.480s	23903.867us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	194.970s	7533.688us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	235.450s	7120.036us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	300.880s	5747.974us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	762.640s	24342.680us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	765.350s	13098.505us	1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	348.450s	8073.516us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	676.810s	13160.042us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	270.170s	4677.122us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	66.110s	2346.880us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	297.970s	5229.894us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	598.410s	12091.701us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	282.440s	6005.635us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	141.760s	3270.644us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	611.060s	13902.590us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	501.280s	6891.733us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	938.690s	10817.220us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1845.660s	29454.162us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	194.720s	3676.214us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	413.810s	5732.165us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	341.700s	10190.310us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	341.700s	10190.310us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	938.690s	10817.220us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	611.060s	13902.590us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	270.170s	4677.122us	1	1	100.00
	chip_sw_pwrmgr_smoketest	260.670s	6160.194us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	209.550s	4171.224us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	276.770s	5667.949us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	226.020s	5041.142us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	1145.750s	14677.512us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	140.270s	2939.631us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	413.810s	5732.165us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1264.010s	8812.988us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	438.360s	4813.296us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	456.490s	5482.034us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	150.700s	3058.908us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	149.220s	3079.010us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	276.770s	5667.949us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	276.770s	5667.949us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	140.870s	2421.333us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	863.190s	13941.607us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	928.720s	13809.882us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	209.550s	4171.224us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	182.210s	3305.903us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	1269.750s	12412.685us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	125.410s	2944.001us	1	1	100.00
chip_rv_dm_lc_disabled				0	1	0.00
	chip_rv_dm_lc_disabled	189.440s	5961.398us	0	1	0.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	451.360s	4515.980us	1	1	100.00
	chip_plic_all_irqs_10	282.780s	3679.725us	1	1	100.00
	chip_plic_all_irqs_20	345.680s	4375.101us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	140.410s	2806.277us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	163.000s	2991.045us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3018.800s	14701.714us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	280.830s	4952.502us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	174.510s	2967.022us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	197.610s	3071.964us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	157.230s	3137.415us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	297.930s	4982.918us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	275.740s	4212.251us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	477.880s	9732.889us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	320.320s	8503.235us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	320.410s	6139.902us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	413.810s	5732.165us	1	1	100.00
	chip_sw_data_integrity_escalation	442.680s	5874.422us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	501.280s	6891.733us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	1032.100s	24434.084us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	161.400s	2859.050us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	231.160s	4251.753us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	273.540s	4543.174us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1032.100s	24434.084us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	1032.100s	24434.084us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2244.320s	21101.238us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2244.320s	21101.238us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	293.740s	6208.996us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	2967.180s	34602.798us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	141.570s	3023.402us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	160.840s	2683.608us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	233.990s	3747.034us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	310.240s	4071.779us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	960.520s	8566.140us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	4917.930s	32160.615us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	2008.470s	12731.788us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	167.750s	3264.489us	1	1	100.00

V2S

2/2 passed

100.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	195.280s	3118.282us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				1	1	100.00
	chip_sw_rv_core_ibex_lockstep_glitch	76.710s	2515.667us	1	1	100.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9553.410s	68227.159us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1157.270s	6314.192us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	216.360s	4081.006us	0	1	0.00
	rom_e2e_jtag_debug_dev	193.280s	3996.611us	0	1	0.00
	rom_e2e_jtag_debug_rma	181.330s	3665.705us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	68.590s	2228.231us	0	1	0.00
	rom_e2e_jtag_inject_dev	79.350s	3539.331us	0	1	0.00
	rom_e2e_jtag_inject_rma	72.670s	2631.217us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	49.283s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	306.410s	4322.219us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	322.930s	3230.959us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	502.990s	3852.809us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1029.440s	9664.175us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	205.640s	2774.274us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	491.100s	5234.341us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	56.930s	2425.767us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	178.600s	3456.179us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	269.850s	5878.682us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	280.020s	5459.229us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	938.690s	10817.220us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	216.360s	4081.006us	0	1	0.00
	rom_e2e_jtag_debug_dev	193.280s	3996.611us	0	1	0.00
	rom_e2e_jtag_debug_rma	181.330s	3665.705us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	291.230s	4671.587us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	413.810s	5732.165us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5298.350s	38385.742us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5298.350s	38385.742us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	148.000s	3503.036us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	334.880s	4358.997us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	2908.590s	19317.527us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	200.550s	2908.384us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	18.090s	10.380us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	5.250s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	141.160s	3148.384us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	144.170s	3165.568us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	235.880s	3867.081us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	7.494s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	209.210s	3669.598us	1	1	100.00
	ate_bootstrap_flash_erase	649.970s	10010.340us	0	1	0.00
	ate_bootstrap_one_frame	6044.380s	43552.540us	1	1	100.00
	ate_bootstrap_disjoint	9491.910s	78985.482us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	49958323035945421345099819133400761477894755957654721547199789604409470388482	None	---- STDOUT ---- ---- STDERR ---- WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	114618165198078336330281669144029107592979278834382417076339209896307720962691	None	Another command (pid=374242) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=447477) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=376568) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	100330794986907815354479503465457276468610876560739828358898573502049004112322	None	Another command (pid=608871) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=562364) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=606999) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	1428302456864173685380150858119444367828560527706236336093844830780978282504	None	Another command (pid=656878) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=657252) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=615593) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	61375452565760786117656877769612042780287788001439648994148247589729049927649	None	Another command (pid=627136) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=630129) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=630841) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	5795978650597171670114368307028788241181252341642432173922683179146016303447	None	---- STDERR ---- Another command (pid=606999) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	92293381103475788216325301514542877142516875925940240896604255152388770362668	None	Another command (pid=452698) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=453676) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=453217) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	106757444409263393551638313550095358646168414899887436569416834182356302702036	None	Another command (pid=566049) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=577844) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=577544) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	11205456082847192367359459829973184845392080882739659484543963930426133843164	None	Another command (pid=568427) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=570211) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=405069) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	83196994407999889492925541680076900809329455272349916390005157931402742975091	None	---- STDERR ---- Another command (pid=454370) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	85780070885402012477608702119260557153392154201114721303495038695350228486336	None	Another command (pid=569319) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=562364) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=606999) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	28941551393605170878853615524119119111308165921239688118237417009833247397972	None	---- STDERR ---- Another command (pid=551519) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=420937) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	61533360666492572582055613856150499527056886475075245451848126761265289797907	None	Another command (pid=562364) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=606999) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=620959) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	35654831310720734945380845828856950650364535653318813709932541514178847245557	None	Another command (pid=599583) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=628027) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=642616) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	101581507780366346676123908333194725145638568169777891811756762232547970283709	None	---- STDERR ---- Another command (pid=589827) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=569319) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	49612513190047368987493701487984027850752509556795821687656483525155282394394	None	Another command (pid=568427) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=570211) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=405069) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	79268749585715723781407090749905218221165019499223610189277599104934048209438	None	Another command (pid=521063) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=433216) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=551519) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	63408777688943593254645651489011027183132188487419498469947145310163514479161	None	Another command (pid=560229) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=465869) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=396938) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	78986287543844045269585689613731510328677378100682490754594023799838670889632	None	Another command (pid=576429) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=454370) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=590552) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	56053197217738399899065231301331353635938109378044094320652371296479530363967	None	Another command (pid=452698) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=453676) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=453217) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	41942518958690438828585782948228314804828991543214523456686405303531959322982	None	Another command (pid=470523) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=544869) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=465869) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	88783558818283877701602005753045042367273740167402164641870735983286431562692	None	Another command (pid=405069) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=590942) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=455567) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	14558646857716550072394622816852854207187567522693888367200195260881301784535	None	---- STDERR ---- Another command (pid=368319) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	69624119409069484012288520267058610743709489360046543766920145921175815552786	None	Another command (pid=374242) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=447477) is running. Waiting for it to complete on the server (server_pid=269319)... Another command (pid=438389) is running. Waiting for it to complete on the server (server_pid=269319)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				7 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	66375140989498390199531753167714437602228909454220331129691828955856966892229	332	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	39198242312085883598557831845796573035225157594633313058934556679751408795274	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	22317746955470632057684607209154754685557267926999341576616846674981691906563	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	59048981678839612772528357100443996700687992197434735155773753503712953281728	319	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	86580125733704094791445807703724846712472854111208217233848368063980062570468	303	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	107768976321169777765272632301384745099808758968319138637698979498847564328900	305	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	109372410774697757923787446832061920522034120169355677635673345910559164661135	307	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	110948746510380830501087888356121090517308458120946508165502481375909973360496	368	UVM_INFO @ 10.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	27879352090485220206226904396958440566234058710406787409390863658955942214832	366	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	24367517286159821868952519131005276706447021902124645609145167976218545218006	366	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	89134983945474673104785103591242293943127268112806048115777019016111164090865	328	UVM_INFO @ 10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	61282697273075561441799184421822015888790738565489112687843080605865260883252	328	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	38389083430055346608386088593419769227463730922751476962476568553061773009363	326	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	60592988884402797891403995515921970218872893603595981672569114421335690080440	369	UVM_INFO @ 10084.785303 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	66263047114703165992626028348422350409263878603549090036117921282167230949473	369	UVM_INFO @ 10823.072660 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	35136543724920835899990319788127095372538883719636237329135393432826292853977	341	UVM_INFO @ 5748.754476 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				3 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	62299508425623306457156819351404909275700203661019124261400514685262738530405	344	UVM_ERROR @ 13902.589500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 13902.589500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	106350592505477758212799372085886208833146641945883822367682674723266777100164	330	UVM_ERROR @ 7120.036000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7120.036000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_aon_timer_wdog_bite_reset	17006032130852819566618056442491740690143040274641742812187424346172482986434	319	UVM_ERROR @ 8073.516000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 8073.516000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	53490571262358192484679445864019419932142278354784193274955896713994123961054	325	UVM_INFO @ 10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	7605992847748503904001046818393147156431717593026006514965806352877638405454	326	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	59559058960728462855330973457538643669656062930364041103992907246101208762628	326	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_ctrl_transition_vseq] max attempt reached to get lc status LcExtClockSwitched!				2 test runs
	chip_sw_lc_ctrl_transition	11480134100061681384202792635983637982381309727703845535739472201728308958551	310	UVM_INFO @ 25832.175171 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_clkmgr_external_clk_src_for_lc	2770976590682794787036484512823272273765184813676046253521518920722947639842	311	UVM_INFO @ 25864.257691 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	63241238832133742802880134592507676190904772880796673737961932563426495246916	318	UVM_ERROR @ 3270.643682 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 3270.643682 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	52704337046920561123106830479382134414514646973705054293221894545544658838679	341	UVM_ERROR @ 12091.701277 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 12091.701277 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				2 test runs
	chip_sw_hmac_multistream	96845014764192258151446310788328320097534839689952927738144085527886357889485	372	UVM_INFO @ 12018.655057 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	114602410623064584724975852384452235652694273527046805702522735325880129261998	336	UVM_INFO @ 20026.890911 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	60276015676229554138453060754377638289895696529433297211430198176312080275062	365	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25686548660842527870627297403923462490483462837954744500580724045181461251959	325	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	65160472336466823047372302706849358401210579730961861557875793893586824923989	368	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	11641281611556782983534875159943620245609777443472754726894025454973572009530	327	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	51212610175291968721160845204744309616686447975540533032335772175322571104558	306	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_spi_passthrough_collision_vseq.sv:183) virtual_sequencer [chip_sw_spi_passthrough_collision_vseq] Compare mismatch				1 test run
	chip_sw_spi_device_pass_through_collision	2519385021662623851266349783777127360826328795459916223353592775994726318494	334	host_rsp: ------------------------------------------------------------------------- Name Type Size Value -------------------------------------------------------------------------
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	39509911041787786654491613126736001300813150825984451655597294139542302514366	314	UVM_INFO @ 3319.279539 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	46876721475342790496055497392925375709845726595273203624210781741361601328930	347	UVM_INFO @ 6961.859079 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	93612321434951864641929829659644572456301288052414061563054036845947694011815	321	UVM_ERROR @ 3456.179256 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 3456.179256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	29203689713114956010639325293389251611361474158514133700346569195552940002334	282	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	114437081596937394871817177819196202174315365311413598207599413460892004133696	308	UVM_ERROR @ 2346.879878 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 2346.879878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	82644598662397860843238330101255809037536442265198119787840072964396117816533	332	UVM_INFO @ 34602.797735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:357)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	1052379956383908179905687027972369260235800675255389220548110014739645247115	307	UVM_INFO @ 2791.354215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	112097260556202391720535000232548373910314740767551710379081908024296396185870	308	UVM_INFO @ 3324.095824 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	19858364440654007617238791450078660020434519839814514371327755776312154906804	None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	113489054563614467529918520377222027707162260265568592845875483551855800763464	343	UVM_INFO @ 4322.219246 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.				1 test run
	chip_sw_rv_dm_access_after_wakeup	70855888578180468345029471965396276835303846120484396732468891133198749319263	334	UVM_INFO @ 12412.685250 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_vseq.sv:660) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [] vs []) addr read out mismatch				1 test run
	chip_rv_dm_lc_disabled	74562495504833714899247523016476280244426820774320405328005349412429258913547	236	UVM_INFO @ 5961.398025 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_idle_load	99442920316703073035263912754522578233742550366504637991155371567000237830041	323	UVM_INFO @ 14368.463189 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_sleep_load	19664539531724365477714821651353756632407563354857914874708748356686702240261	342	UVM_INFO @ 14845.221452 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	86128134463343238951427708346876229509623297212476771677637730192455764796859	327	UVM_INFO @ 10019.600086 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	53969613356257762790173160677848998425570409625168792977751048871505263380393	272	UVM_INFO @ 10010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_exception_c	109140772736291080581473853964134683766291523894145768119604708465389831554720	319	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 5694.174633 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_output	30953153392782628236074500790095599353821511537430095593320011148822274235739	312	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 11625.750785 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	29551146967957927961364425969288213285750571155129234456473367628760693804984	325	UVM_INFO @ 10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	92466187520602219743475662479307845079318086461871559355072893292732242314519	326	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_meas	109872607487985461164289315908671312033618716333617224108663712754991832271937	319	UVM_INFO @ 16499.322098 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	32594285863167298241853978420987736742616801647181231986575253497454987498741	332	UVM_ERROR @ 4530.156876 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4530.156876 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_csr_mem_rw_with_rand_reset	106108670902166128949817259515275894122960133899280419323902338550351370045467	224	TL item was: req: (cip_tl_seq_item@30288) { a_addr: 'h105cc a_data: 'h5a8f1732 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h11 a_opcode: 'h4 a_user: 'h1929f d_param: 'h0 d_source: 'h11 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2405.929215 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---