Simulation Results: clkmgr

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 92.46 %
  • code
  • 98.08 %
  • assert
  • 95.76 %
  • func
  • 83.53 %
  • line
  • 98.85 %
  • branch
  • 98.48 %
  • cond
  • 93.86 %
  • toggle
  • 99.19 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
83.33%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
clkmgr_smoke 0.820s 58.879us 1 1 100.00
csr_hw_reset 1 1 100.00
clkmgr_csr_hw_reset 0.880s 49.828us 1 1 100.00
csr_rw 1 1 100.00
clkmgr_csr_rw 1.000s 23.762us 1 1 100.00
csr_bit_bash 1 1 100.00
clkmgr_csr_bit_bash 3.490s 427.977us 1 1 100.00
csr_aliasing 1 1 100.00
clkmgr_csr_aliasing 0.950s 43.199us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
clkmgr_csr_mem_rw_with_rand_reset 0.900s 27.974us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
clkmgr_csr_rw 1.000s 23.762us 1 1 100.00
clkmgr_csr_aliasing 0.950s 43.199us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
peri_enables 1 1 100.00
clkmgr_peri 0.720s 41.909us 1 1 100.00
trans_enables 1 1 100.00
clkmgr_trans 0.990s 106.685us 1 1 100.00
extclk 1 1 100.00
clkmgr_extclk 0.950s 104.685us 1 1 100.00
clk_status 1 1 100.00
clkmgr_clk_status 0.700s 23.399us 1 1 100.00
jitter 1 1 100.00
clkmgr_smoke 0.820s 58.879us 1 1 100.00
frequency 1 1 100.00
clkmgr_frequency 6.340s 2117.007us 1 1 100.00
frequency_timeout 1 1 100.00
clkmgr_frequency_timeout 5.190s 1465.338us 1 1 100.00
frequency_overflow 1 1 100.00
clkmgr_frequency 6.340s 2117.007us 1 1 100.00
stress_all 1 1 100.00
clkmgr_stress_all 0.910s 89.586us 1 1 100.00
alert_test 1 1 100.00
clkmgr_alert_test 0.730s 38.651us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
clkmgr_tl_errors 1.540s 110.404us 1 1 100.00
tl_d_illegal_access 1 1 100.00
clkmgr_tl_errors 1.540s 110.404us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
clkmgr_csr_hw_reset 0.880s 49.828us 1 1 100.00
clkmgr_csr_rw 1.000s 23.762us 1 1 100.00
clkmgr_csr_aliasing 0.950s 43.199us 1 1 100.00
clkmgr_same_csr_outstanding 1.100s 102.189us 1 1 100.00
tl_d_partial_access 4 4 100.00
clkmgr_csr_hw_reset 0.880s 49.828us 1 1 100.00
clkmgr_csr_rw 1.000s 23.762us 1 1 100.00
clkmgr_csr_aliasing 0.950s 43.199us 1 1 100.00
clkmgr_same_csr_outstanding 1.100s 102.189us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
clkmgr_sec_cm 42.260s 10090.726us 0 1 0.00
clkmgr_tl_intg_err 28.770s 10079.728us 0 1 0.00
shadow_reg_update_error 1 1 100.00
clkmgr_shadow_reg_errors 1.680s 267.469us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
clkmgr_shadow_reg_errors 1.680s 267.469us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
clkmgr_shadow_reg_errors 1.680s 267.469us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
clkmgr_shadow_reg_errors 1.680s 267.469us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
clkmgr_shadow_reg_errors_with_csr_rw 1.910s 325.334us 1 1 100.00
sec_cm_bus_integrity 0 1 0.00
clkmgr_tl_intg_err 28.770s 10079.728us 0 1 0.00
sec_cm_meas_clk_bkgn_chk 1 1 100.00
clkmgr_frequency 6.340s 2117.007us 1 1 100.00
sec_cm_timeout_clk_bkgn_chk 1 1 100.00
clkmgr_frequency_timeout 5.190s 1465.338us 1 1 100.00
sec_cm_meas_config_shadow 1 1 100.00
clkmgr_shadow_reg_errors 1.680s 267.469us 1 1 100.00
sec_cm_idle_intersig_mubi 1 1 100.00
clkmgr_idle_intersig_mubi 0.830s 56.137us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
clkmgr_lc_ctrl_intersig_mubi 1.300s 284.889us 1 1 100.00
sec_cm_lc_ctrl_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_lc_clk_byp_req_intersig_mubi 0.780s 29.811us 1 1 100.00
sec_cm_clk_handshake_intersig_mubi 1 1 100.00
clkmgr_clk_handshake_intersig_mubi 0.960s 31.344us 1 1 100.00
sec_cm_div_intersig_mubi 1 1 100.00
clkmgr_div_intersig_mubi 0.900s 30.183us 1 1 100.00
sec_cm_jitter_config_mubi 1 1 100.00
clkmgr_csr_rw 1.000s 23.762us 1 1 100.00
sec_cm_idle_ctr_redun 0 1 0.00
clkmgr_sec_cm 42.260s 10090.726us 0 1 0.00
sec_cm_meas_config_regwen 1 1 100.00
clkmgr_csr_rw 1.000s 23.762us 1 1 100.00
sec_cm_clk_ctrl_config_regwen 1 1 100.00
clkmgr_csr_rw 1.000s 23.762us 1 1 100.00
prim_count_check 0 1 0.00
clkmgr_sec_cm 42.260s 10090.726us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
regwen 1 1 100.00
clkmgr_regwen 4.260s 1547.633us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
clkmgr_stress_all_with_rand_reset 14.530s 2199.816us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1077) virtual_sequencer [clkmgr_common_vseq] Timeout waiting for end of ack for alert fatal_fault 2 test runs
clkmgr_sec_cm 12544262234731148990114485142223085924905263782909828135837492029414196199789 103
UVM_INFO @ 10090725752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
clkmgr_tl_intg_err 43279803852852207898197727885164973110356260538019562026237398090791888736960 136
UVM_INFO @ 10079728296 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---