Simulation Results: csrng

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 89.17 %
  • code
  • 92.48 %
  • assert
  • 95.20 %
  • func
  • 79.84 %
  • block
  • 97.16 %
  • line
  • 97.94 %
  • branch
  • 93.02 %
  • toggle
  • 93.24 %
  • FSM
  • 85.71 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 88.902us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 2.000s 16.231us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 21.004us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 36.000s 2888.215us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 5.000s 150.891us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 2.000s 29.551us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 21.004us 1 1 100.00
csrng_csr_aliasing 5.000s 150.891us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
alerts 1 1 100.00
csrng_alert 5.000s 136.939us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 4.000s 158.798us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 4.000s 158.798us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 442.000s 11726.347us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 1.000s 35.900us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 2.000s 58.823us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 14.000s 1339.555us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 14.000s 1339.555us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 2.000s 16.231us 1 1 100.00
csrng_csr_rw 2.000s 21.004us 1 1 100.00
csrng_csr_aliasing 5.000s 150.891us 1 1 100.00
csrng_same_csr_outstanding 3.000s 124.285us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 2.000s 16.231us 1 1 100.00
csrng_csr_rw 2.000s 21.004us 1 1 100.00
csrng_csr_aliasing 5.000s 150.891us 1 1 100.00
csrng_same_csr_outstanding 3.000s 124.285us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_sec_cm 3.000s 67.447us 1 1 100.00
csrng_tl_intg_err 3.000s 62.806us 1 1 100.00
sec_cm_config_regwen 1 2 50.00
csrng_regwen 1.000s 9.297us 0 1 0.00
csrng_csr_rw 2.000s 21.004us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 5.000s 136.939us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 442.000s 11726.347us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
csrng_sec_cm 3.000s 67.447us 1 1 100.00
sec_cm_cmd_stage_fsm_sparse 3 3 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
csrng_sec_cm 3.000s 67.447us 1 1 100.00
sec_cm_ctr_drbg_fsm_sparse 3 3 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
csrng_sec_cm 3.000s 67.447us 1 1 100.00
sec_cm_ctr_drbg_ctr_redun 3 3 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
csrng_sec_cm 3.000s 67.447us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
csrng_sec_cm 3.000s 67.447us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 5.000s 136.939us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 442.000s 11726.347us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 5.000s 136.939us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 3.000s 62.806us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
csrng_sec_cm 3.000s 67.447us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
csrng_sec_cm 3.000s 67.447us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 7.000s 440.020us 1 1 100.00
csrng_err 2.000s 25.903us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
csrng_stress_all_with_rand_reset 3601.000s 0.000us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (csrng_regwen_vseq.sv:62) virtual_sequencer [csrng_regwen_vseq] Was unable to write INT_STATE_READ_ENABLE 1 test run
csrng_regwen 72990088044698928334124906839232398679042363644927604431186697666911896947599 99
UVM_INFO @ 9296787 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
Job timed out after * minutes 1 test run
csrng_stress_all_with_rand_reset 36452582375539498626606792791585344488713660526165354073774879279584990981499 None