Simulation Results: edn/edn0

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 84.14 %
  • code
  • 79.10 %
  • assert
  • 94.36 %
  • func
  • 78.97 %
  • line
  • 96.79 %
  • branch
  • 88.70 %
  • cond
  • 84.04 %
  • toggle
  • 78.12 %
  • FSM
  • 47.85 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 43.262us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.900s 44.983us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 25.463us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.970s 572.884us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.120s 19.958us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.520s 30.268us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 25.463us 1 1 100.00
edn_csr_aliasing 1.120s 19.958us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.290s 44.720us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.290s 44.720us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.290s 44.720us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.800s 29.276us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.070s 46.418us 1 1 100.00
errs 1 1 100.00
edn_err 0.950s 20.313us 1 1 100.00
disable 2 2 100.00
edn_disable 0.800s 18.087us 1 1 100.00
edn_disable_auto_req_mode 0.970s 55.898us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.190s 136.348us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.890s 18.875us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.930s 18.342us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.780s 121.221us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.780s 121.221us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.900s 44.983us 1 1 100.00
edn_csr_rw 0.810s 25.463us 1 1 100.00
edn_csr_aliasing 1.120s 19.958us 1 1 100.00
edn_same_csr_outstanding 1.220s 38.418us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.900s 44.983us 1 1 100.00
edn_csr_rw 0.810s 25.463us 1 1 100.00
edn_csr_aliasing 1.120s 19.958us 1 1 100.00
edn_same_csr_outstanding 1.220s 38.418us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 6.930s 2228.182us 1 1 100.00
edn_tl_intg_err 1.960s 136.888us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 16.267us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.070s 46.418us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.930s 2228.182us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 6.930s 2228.182us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 6.930s 2228.182us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 6.930s 2228.182us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.070s 46.418us 1 1 100.00
edn_sec_cm 6.930s 2228.182us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.070s 46.418us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.960s 136.888us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 41.940s 10805.941us 1 1 100.00