Simulation Results: edn/edn1

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 86.46 %
  • code
  • 82.38 %
  • assert
  • 98.44 %
  • func
  • 78.57 %
  • line
  • 98.03 %
  • branch
  • 93.29 %
  • cond
  • 87.92 %
  • toggle
  • 87.23 %
  • FSM
  • 45.45 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.820s 54.744us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.850s 24.501us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.810s 38.586us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.980s 2301.606us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.280s 308.045us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.900s 68.138us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.810s 38.586us 1 1 100.00
edn_csr_aliasing 1.280s 308.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 0.870s 89.795us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 0.870s 89.795us 1 1 100.00
genbits 1 1 100.00
edn_genbits 0.870s 89.795us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.850s 19.929us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.020s 68.430us 1 1 100.00
errs 1 1 100.00
edn_err 1.010s 23.293us 1 1 100.00
disable 2 2 100.00
edn_disable 0.750s 40.781us 1 1 100.00
edn_disable_auto_req_mode 0.980s 60.914us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 2.660s 822.401us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.770s 31.937us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.800s 47.182us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.060s 47.524us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.060s 47.524us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.850s 24.501us 1 1 100.00
edn_csr_rw 0.810s 38.586us 1 1 100.00
edn_csr_aliasing 1.280s 308.045us 1 1 100.00
edn_same_csr_outstanding 0.910s 69.236us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.850s 24.501us 1 1 100.00
edn_csr_rw 0.810s 38.586us 1 1 100.00
edn_csr_aliasing 1.280s 308.045us 1 1 100.00
edn_same_csr_outstanding 0.910s 69.236us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.260s 1077.213us 1 1 100.00
edn_tl_intg_err 1.580s 143.439us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.050s 28.840us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.020s 68.430us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.260s 1077.213us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.260s 1077.213us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.260s 1077.213us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.260s 1077.213us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.020s 68.430us 1 1 100.00
edn_sec_cm 3.260s 1077.213us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.020s 68.430us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.580s 143.439us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 18.950s 1227.334us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [edn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
edn_stress_all_with_rand_reset 53578999691807960764931440436166290199853337488458518788830899141453272132487 220
UVM_INFO @ 1227334062 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---