| V1 |
|
83.33% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
50.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| entropy_src_smoke | 1.000s | 33.295us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| entropy_src_csr_hw_reset | 1.000s | 78.223us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 19.408us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| entropy_src_csr_bit_bash | 6.000s | 2674.954us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| entropy_src_csr_aliasing | 2.000s | 39.034us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_csr_mem_rw_with_rand_reset | 1.000s | 43.445us | 0 | 1 | 0.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| entropy_src_csr_rw | 1.000s | 19.408us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 39.034us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| firmware | 3 | 3 | 100.00 | |||
| entropy_src_smoke | 1.000s | 33.295us | 1 | 1 | 100.00 | |
| entropy_src_rng | 26.000s | 13096.712us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 13.000s | 14481.466us | 1 | 1 | 100.00 | |
| firmware_mode | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov | 13.000s | 14481.466us | 1 | 1 | 100.00 | |
| rng_mode | 1 | 1 | 100.00 | |||
| entropy_src_rng | 26.000s | 13096.712us | 1 | 1 | 100.00 | |
| rng_max_rate | 1 | 1 | 100.00 | |||
| entropy_src_rng_max_rate | 340.000s | 13014.755us | 1 | 1 | 100.00 | |
| health_checks | 1 | 1 | 100.00 | |||
| entropy_src_rng | 26.000s | 13096.712us | 1 | 1 | 100.00 | |
| conditioning | 1 | 1 | 100.00 | |||
| entropy_src_rng | 26.000s | 13096.712us | 1 | 1 | 100.00 | |
| interrupts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 26.000s | 13096.712us | 1 | 1 | 100.00 | |
| entropy_src_intr | 9.000s | 1391.430us | 1 | 1 | 100.00 | |
| alerts | 2 | 2 | 100.00 | |||
| entropy_src_rng | 26.000s | 13096.712us | 1 | 1 | 100.00 | |
| entropy_src_functional_alerts | 4.000s | 184.151us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| entropy_src_stress_all | 198.000s | 14154.814us | 1 | 1 | 100.00 | |
| functional_errors | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 51.956us | 1 | 1 | 100.00 | |
| firmware_ov_read_contiguous_data | 1 | 1 | 100.00 | |||
| entropy_src_fw_ov_contiguous | 2.000s | 41.411us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| entropy_src_intr_test | 2.000s | 23.319us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| entropy_src_alert_test | 2.000s | 31.894us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 3.000s | 40.819us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| entropy_src_tl_errors | 3.000s | 40.819us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 1.000s | 78.223us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 19.408us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 39.034us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 2.000s | 50.118us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| entropy_src_csr_hw_reset | 1.000s | 78.223us | 1 | 1 | 100.00 | |
| entropy_src_csr_rw | 1.000s | 19.408us | 1 | 1 | 100.00 | |
| entropy_src_csr_aliasing | 2.000s | 39.034us | 1 | 1 | 100.00 | |
| entropy_src_same_csr_outstanding | 2.000s | 50.118us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| entropy_src_sec_cm | 2.000s | 300.733us | 1 | 1 | 100.00 | |
| entropy_src_tl_intg_err | 4.000s | 178.520us | 1 | 1 | 100.00 | |
| sec_cm_config_regwen | 2 | 2 | 100.00 | |||
| entropy_src_rng | 26.000s | 13096.712us | 1 | 1 | 100.00 | |
| entropy_src_cfg_regwen | 2.000s | 20.234us | 1 | 1 | 100.00 | |
| sec_cm_config_mubi | 1 | 1 | 100.00 | |||
| entropy_src_rng | 26.000s | 13096.712us | 1 | 1 | 100.00 | |
| sec_cm_config_redun | 1 | 1 | 100.00 | |||
| entropy_src_rng | 26.000s | 13096.712us | 1 | 1 | 100.00 | |
| sec_cm_intersig_mubi | 2 | 2 | 100.00 | |||
| entropy_src_rng | 26.000s | 13096.712us | 1 | 1 | 100.00 | |
| entropy_src_fw_ov | 13.000s | 14481.466us | 1 | 1 | 100.00 | |
| sec_cm_main_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 51.956us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 300.733us | 1 | 1 | 100.00 | |
| sec_cm_ack_sm_fsm_sparse | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 51.956us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 300.733us | 1 | 1 | 100.00 | |
| sec_cm_rng_bkgn_chk | 1 | 1 | 100.00 | |||
| entropy_src_rng | 26.000s | 13096.712us | 1 | 1 | 100.00 | |
| sec_cm_fifo_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 51.956us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 300.733us | 1 | 1 | 100.00 | |
| sec_cm_ctr_redun | 2 | 2 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 51.956us | 1 | 1 | 100.00 | |
| entropy_src_sec_cm | 2.000s | 300.733us | 1 | 1 | 100.00 | |
| sec_cm_ctr_local_esc | 1 | 1 | 100.00 | |||
| entropy_src_functional_errors | 3.000s | 51.956us | 1 | 1 | 100.00 | |
| sec_cm_esfinal_rdata_bus_consistency | 1 | 1 | 100.00 | |||
| entropy_src_functional_alerts | 4.000s | 184.151us | 1 | 1 | 100.00 | |
| sec_cm_tile_link_bus_integrity | 1 | 1 | 100.00 | |||
| entropy_src_tl_intg_err | 4.000s | 178.520us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| external_health_tests | 1 | 1 | 100.00 | |||
| entropy_src_rng_with_xht_rsps | 202.000s | 14095.162us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 0 | 1 | 0.00 | |||
| entropy_src_stress_all_with_rand_reset | 4.000s | 190.164us | 0 | 1 | 0.00 | |
| Test | seed | line | log context | |
|---|---|---|---|---|
| UVM_WARNING (uvm_reg_field.svh:1186) [RegModel] Trying to predict value of field 'observe_fifo_depth' while register 'entropy_src_reg_block.observe_fifo_depth' is being accessed | 1 test run | |||
| entropy_src_stress_all_with_rand_reset | 87373145395286849213057217539364575281998616716406693186312666662418395090883 | 116 |
UVM_FATAL @ 190163556 ps: (entropy_src_scoreboard.sv:1601) [uvm_test_top.env.scoreboard] Check failed (ral.observe_fifo_depth.observe_fifo_depth.predict( ral.observe_fifo_depth.observe_fifo_depth.get_mirrored_value()-1, .kind(UVM_PREDICT_DIRECT)))
UVM_INFO @ 190163556 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|
| UVM_ERROR (entropy_src_base_vseq.sv:83) virtual_sequencer [mirror] Failed to mirror bucket_total_fails | 1 test run | |||
| entropy_src_csr_mem_rw_with_rand_reset | 73194319444529645012272786581126114291630032712986318672009973895469754185354 | 113 |
UVM_INFO @ 43444877 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
|
|