Simulation Results: flash_ctrl

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 95.59 %
  • code
  • 93.92 %
  • assert
  • 96.94 %
  • func
  • 95.91 %
  • line
  • 95.98 %
  • branch
  • 97.06 %
  • cond
  • 93.88 %
  • toggle
  • 98.34 %
  • FSM
  • 84.35 %
Validation stages
V1
100.00%
V2
98.28%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
flash_ctrl_smoke 32.470s 47.070us 1 1 100.00
smoke_hw 1 1 100.00
flash_ctrl_smoke_hw 9.570s 60.705us 1 1 100.00
csr_hw_reset 1 1 100.00
flash_ctrl_csr_hw_reset 15.610s 111.704us 1 1 100.00
csr_rw 1 1 100.00
flash_ctrl_csr_rw 6.960s 111.102us 1 1 100.00
csr_bit_bash 1 1 100.00
flash_ctrl_csr_bit_bash 61.820s 16313.685us 1 1 100.00
csr_aliasing 1 1 100.00
flash_ctrl_csr_aliasing 20.860s 1789.627us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
flash_ctrl_csr_mem_rw_with_rand_reset 9.010s 125.647us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
flash_ctrl_csr_rw 6.960s 111.102us 1 1 100.00
flash_ctrl_csr_aliasing 20.860s 1789.627us 1 1 100.00
mem_walk 1 1 100.00
flash_ctrl_mem_walk 5.520s 32.283us 1 1 100.00
mem_partial_access 1 1 100.00
flash_ctrl_mem_partial_access 5.650s 78.868us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sw_op 1 1 100.00
flash_ctrl_sw_op 9.600s 52.914us 1 1 100.00
host_read_direct 1 1 100.00
flash_ctrl_host_dir_rd 11.500s 57.737us 1 1 100.00
rma_hw_if 3 3 100.00
flash_ctrl_hw_rma 1181.500s 209780.471us 1 1 100.00
flash_ctrl_hw_rma_reset 637.750s 160189.573us 1 1 100.00
flash_ctrl_lcmgr_intg 5.680s 78.552us 1 1 100.00
host_controller_arb 1 1 100.00
flash_ctrl_host_ctrl_arb 1057.550s 496357.104us 1 1 100.00
erase_suspend 1 1 100.00
flash_ctrl_erase_suspend 161.240s 1436.168us 1 1 100.00
program_reset 1 1 100.00
flash_ctrl_prog_reset 5.870s 20.672us 1 1 100.00
full_memory_access 1 1 100.00
flash_ctrl_full_mem_access 2501.360s 216734.903us 1 1 100.00
rd_buff_eviction 1 1 100.00
flash_ctrl_rd_buff_evict 38.130s 127.052us 1 1 100.00
rd_buff_eviction_w_ecc 3 3 100.00
flash_ctrl_rw_evict 13.340s 237.230us 1 1 100.00
flash_ctrl_rw_evict_all_en 13.200s 30.137us 1 1 100.00
flash_ctrl_re_evict 14.890s 259.674us 1 1 100.00
host_arb 1 1 100.00
flash_ctrl_phy_arb 128.850s 2745.033us 1 1 100.00
host_interleave 1 1 100.00
flash_ctrl_phy_arb 128.850s 2745.033us 1 1 100.00
memory_protection 1 1 100.00
flash_ctrl_mp_regions 172.780s 12543.644us 1 1 100.00
fetch_code 1 1 100.00
flash_ctrl_fetch_code 12.580s 491.211us 1 1 100.00
all_partitions 1 1 100.00
flash_ctrl_rand_ops 285.790s 367.472us 1 1 100.00
error_mp 1 1 100.00
flash_ctrl_error_mp 463.160s 16992.382us 1 1 100.00
error_prog_win 1 1 100.00
flash_ctrl_error_prog_win 319.330s 1460.608us 1 1 100.00
error_prog_type 1 1 100.00
flash_ctrl_error_prog_type 989.680s 723.358us 1 1 100.00
error_read_seed 1 1 100.00
flash_ctrl_hw_read_seed_err 6.860s 28.089us 1 1 100.00
read_write_overflow 1 1 100.00
flash_ctrl_oversize_error 120.900s 6380.168us 1 1 100.00
flash_ctrl_disable 1 1 100.00
flash_ctrl_disable 9.090s 62.742us 1 1 100.00
flash_ctrl_connect 1 1 100.00
flash_ctrl_connect 5.720s 85.804us 1 1 100.00
stress_all 1 1 100.00
flash_ctrl_stress_all 408.880s 896.395us 1 1 100.00
secret_partition 2 2 100.00
flash_ctrl_hw_sec_otp 23.710s 579.957us 1 1 100.00
flash_ctrl_otp_reset 55.540s 223.855us 1 1 100.00
isolation_partition 1 1 100.00
flash_ctrl_hw_rma 1181.500s 209780.471us 1 1 100.00
interrupts 4 4 100.00
flash_ctrl_intr_rd 111.620s 10935.616us 1 1 100.00
flash_ctrl_intr_wr 42.380s 2654.759us 1 1 100.00
flash_ctrl_intr_rd_slow_flash 72.140s 23004.938us 1 1 100.00
flash_ctrl_intr_wr_slow_flash 131.180s 27142.079us 1 1 100.00
invalid_op 1 1 100.00
flash_ctrl_invalid_op 41.720s 7591.797us 1 1 100.00
mid_op_rst 1 1 100.00
flash_ctrl_mid_op_rst 35.200s 3996.118us 1 1 100.00
double_bit_err 5 5 100.00
flash_ctrl_read_word_sweep_derr 10.250s 324.750us 1 1 100.00
flash_ctrl_ro_derr 107.660s 4042.950us 1 1 100.00
flash_ctrl_rw_derr 121.040s 1742.634us 1 1 100.00
flash_ctrl_derr_detect 96.090s 2901.783us 1 1 100.00
flash_ctrl_integrity 314.370s 18061.942us 1 1 100.00
single_bit_err 3 3 100.00
flash_ctrl_read_word_sweep_serr 10.000s 58.312us 1 1 100.00
flash_ctrl_ro_serr 90.840s 11620.411us 1 1 100.00
flash_ctrl_rw_serr 140.670s 3989.165us 1 1 100.00
singlebit_err_counter 1 1 100.00
flash_ctrl_serr_counter 49.950s 6196.999us 1 1 100.00
singlebit_err_address 1 1 100.00
flash_ctrl_serr_address 37.550s 2565.306us 1 1 100.00
scramble 4 5 80.00
flash_ctrl_wo 2155.610s 200000.000us 0 1 0.00
flash_ctrl_write_word_sweep 6.370s 43.006us 1 1 100.00
flash_ctrl_read_word_sweep 6.140s 107.457us 1 1 100.00
flash_ctrl_ro 68.670s 2698.983us 1 1 100.00
flash_ctrl_rw 330.890s 16131.591us 1 1 100.00
filesystem_support 1 1 100.00
flash_ctrl_fs_sup 22.480s 1443.415us 1 1 100.00
rma_write_process_error 2 2 100.00
flash_ctrl_rma_err 522.220s 80721.317us 1 1 100.00
flash_ctrl_hw_prog_rma_wipe_err 38.490s 10046.185us 1 1 100.00
alert_test 1 1 100.00
flash_ctrl_alert_test 6.100s 26.462us 1 1 100.00
intr_test 1 1 100.00
flash_ctrl_intr_test 5.670s 30.713us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
flash_ctrl_tl_errors 9.730s 131.001us 1 1 100.00
tl_d_illegal_access 1 1 100.00
flash_ctrl_tl_errors 9.730s 131.001us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.610s 111.704us 1 1 100.00
flash_ctrl_csr_rw 6.960s 111.102us 1 1 100.00
flash_ctrl_csr_aliasing 20.860s 1789.627us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.450s 233.588us 1 1 100.00
tl_d_partial_access 4 4 100.00
flash_ctrl_csr_hw_reset 15.610s 111.704us 1 1 100.00
flash_ctrl_csr_rw 6.960s 111.102us 1 1 100.00
flash_ctrl_csr_aliasing 20.860s 1789.627us 1 1 100.00
flash_ctrl_same_csr_outstanding 7.450s 233.588us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
flash_ctrl_shadow_reg_errors 13.690s 119.665us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
flash_ctrl_shadow_reg_errors 13.690s 119.665us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
flash_ctrl_shadow_reg_errors 13.690s 119.665us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
flash_ctrl_shadow_reg_errors 13.690s 119.665us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
flash_ctrl_shadow_reg_errors_with_csr_rw 16.030s 765.026us 1 1 100.00
tl_intg_err 2 2 100.00
flash_ctrl_sec_cm 1724.310s 1648.161us 1 1 100.00
flash_ctrl_tl_intg_err 200.140s 387.184us 1 1 100.00
sec_cm_reg_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 200.140s 387.184us 1 1 100.00
sec_cm_host_bus_integrity 1 1 100.00
flash_ctrl_tl_intg_err 200.140s 387.184us 1 1 100.00
sec_cm_mem_bus_integrity 2 2 100.00
flash_ctrl_rd_intg 15.410s 70.454us 1 1 100.00
flash_ctrl_wr_intg 6.510s 93.190us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
flash_ctrl_smoke 32.470s 47.070us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 4 4 100.00
flash_ctrl_otp_reset 55.540s 223.855us 1 1 100.00
flash_ctrl_disable 9.090s 62.742us 1 1 100.00
flash_ctrl_sec_info_access 31.840s 1979.360us 1 1 100.00
flash_ctrl_connect 5.720s 85.804us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
flash_ctrl_config_regwen 6.200s 78.713us 1 1 100.00
sec_cm_data_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.960s 111.102us 1 1 100.00
sec_cm_data_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 13.690s 119.665us 1 1 100.00
sec_cm_info_regions_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.960s 111.102us 1 1 100.00
sec_cm_info_regions_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 13.690s 119.665us 1 1 100.00
sec_cm_bank_config_regwen 1 1 100.00
flash_ctrl_csr_rw 6.960s 111.102us 1 1 100.00
sec_cm_bank_config_shadow 1 1 100.00
flash_ctrl_shadow_reg_errors 13.690s 119.665us 1 1 100.00
sec_cm_mem_ctrl_global_esc 1 1 100.00
flash_ctrl_disable 9.090s 62.742us 1 1 100.00
sec_cm_mem_ctrl_local_esc 2 2 100.00
flash_ctrl_rd_intg 15.410s 70.454us 1 1 100.00
flash_ctrl_access_after_disable 6.000s 22.245us 1 1 100.00
sec_cm_mem_addr_infection 1 1 100.00
flash_ctrl_host_addr_infection 12.940s 28.602us 1 1 100.00
sec_cm_mem_disable_config_mubi 1 1 100.00
flash_ctrl_disable 9.090s 62.742us 1 1 100.00
sec_cm_exec_config_redun 1 1 100.00
flash_ctrl_fetch_code 12.580s 491.211us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
flash_ctrl_rw 330.890s 16131.591us 1 1 100.00
sec_cm_mem_integrity 3 3 100.00
flash_ctrl_rw_serr 140.670s 3989.165us 1 1 100.00
flash_ctrl_rw_derr 121.040s 1742.634us 1 1 100.00
flash_ctrl_integrity 314.370s 18061.942us 1 1 100.00
sec_cm_rma_entry_mem_sec_wipe 1 1 100.00
flash_ctrl_hw_rma 1181.500s 209780.471us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1724.310s 1648.161us 1 1 100.00
sec_cm_phy_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1724.310s 1648.161us 1 1 100.00
sec_cm_phy_prog_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1724.310s 1648.161us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1724.310s 1648.161us 1 1 100.00
sec_cm_phy_arbiter_ctrl_redun 1 1 100.00
flash_ctrl_phy_arb_redun 8.790s 865.000us 1 1 100.00
sec_cm_phy_host_grant_ctrl_consistency 1 1 100.00
flash_ctrl_phy_host_grant_err 5.950s 23.026us 1 1 100.00
sec_cm_phy_ack_ctrl_consistency 1 1 100.00
flash_ctrl_phy_ack_consistency 6.480s 34.829us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
flash_ctrl_sec_cm 1724.310s 1648.161us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1724.310s 1648.161us 1 1 100.00
sec_cm_prog_tl_lc_gate_fsm_sparse 1 1 100.00
flash_ctrl_sec_cm 1724.310s 1648.161us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
asymmetric_read_path 1 1 100.00
flash_ctrl_rd_ooo 19.300s 140.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
flash_ctrl_basic_rw 50.250s 1383.630us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ns hit, indicating a probable testbench issue 1 test run
flash_ctrl_wo 108059628889137797126735560334899458151700825240649449129188141309800891184929 113
UVM_INFO @ 200000000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---