Simulation Results: hmac

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 80.14 %
  • code
  • 98.00 %
  • assert
  • 97.60 %
  • func
  • 44.82 %
  • line
  • 99.74 %
  • branch
  • 99.67 %
  • cond
  • 96.46 %
  • toggle
  • 100.00 %
  • FSM
  • 94.12 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 1.800s 209.521us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.830s 103.355us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.720s 49.154us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 8.730s 4684.279us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.090s 276.324us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.410s 64.881us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.720s 49.154us 1 1 100.00
hmac_csr_aliasing 2.090s 276.324us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 50.660s 6968.777us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 11.520s 2056.650us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 172.720s 7753.420us 1 1 100.00
hmac_test_sha384_vectors 411.580s 33416.612us 1 1 100.00
hmac_test_sha512_vectors 19.930s 683.472us 1 1 100.00
hmac_test_hmac256_vectors 9.970s 445.722us 1 1 100.00
hmac_test_hmac384_vectors 7.670s 610.769us 1 1 100.00
hmac_test_hmac512_vectors 11.830s 3063.856us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 11.510s 11485.217us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 164.380s 4024.394us 1 1 100.00
error 1 1 100.00
hmac_error 15.840s 8517.676us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 74.640s 8414.703us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 1.800s 209.521us 1 1 100.00
hmac_long_msg 50.660s 6968.777us 1 1 100.00
hmac_back_pressure 11.520s 2056.650us 1 1 100.00
hmac_datapath_stress 164.380s 4024.394us 1 1 100.00
hmac_burst_wr 11.510s 11485.217us 1 1 100.00
hmac_stress_all 1315.410s 22519.289us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 1.800s 209.521us 1 1 100.00
hmac_long_msg 50.660s 6968.777us 1 1 100.00
hmac_back_pressure 11.520s 2056.650us 1 1 100.00
hmac_datapath_stress 164.380s 4024.394us 1 1 100.00
hmac_wipe_secret 74.640s 8414.703us 1 1 100.00
hmac_test_sha256_vectors 172.720s 7753.420us 1 1 100.00
hmac_test_sha384_vectors 411.580s 33416.612us 1 1 100.00
hmac_test_sha512_vectors 19.930s 683.472us 1 1 100.00
hmac_test_hmac256_vectors 9.970s 445.722us 1 1 100.00
hmac_test_hmac384_vectors 7.670s 610.769us 1 1 100.00
hmac_test_hmac512_vectors 11.830s 3063.856us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 1.800s 209.521us 1 1 100.00
hmac_long_msg 50.660s 6968.777us 1 1 100.00
hmac_back_pressure 11.520s 2056.650us 1 1 100.00
hmac_datapath_stress 164.380s 4024.394us 1 1 100.00
hmac_burst_wr 11.510s 11485.217us 1 1 100.00
hmac_error 15.840s 8517.676us 1 1 100.00
hmac_wipe_secret 74.640s 8414.703us 1 1 100.00
hmac_test_sha256_vectors 172.720s 7753.420us 1 1 100.00
hmac_test_sha384_vectors 411.580s 33416.612us 1 1 100.00
hmac_test_sha512_vectors 19.930s 683.472us 1 1 100.00
hmac_test_hmac256_vectors 9.970s 445.722us 1 1 100.00
hmac_test_hmac384_vectors 7.670s 610.769us 1 1 100.00
hmac_test_hmac512_vectors 11.830s 3063.856us 1 1 100.00
hmac_stress_all 1315.410s 22519.289us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1315.410s 22519.289us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.590s 14.708us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.680s 16.791us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.880s 1403.648us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.880s 1403.648us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.830s 103.355us 1 1 100.00
hmac_csr_rw 0.720s 49.154us 1 1 100.00
hmac_csr_aliasing 2.090s 276.324us 1 1 100.00
hmac_same_csr_outstanding 1.340s 70.216us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.830s 103.355us 1 1 100.00
hmac_csr_rw 0.720s 49.154us 1 1 100.00
hmac_csr_aliasing 2.090s 276.324us 1 1 100.00
hmac_same_csr_outstanding 1.340s 70.216us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 0.900s 65.514us 1 1 100.00
hmac_tl_intg_err 2.520s 183.300us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 2.520s 183.300us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 1.800s 209.521us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 2.110s 217.148us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 234.720s 21490.471us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 0.660s 8.092us 1 1 100.00