Simulation Results: keymgr

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 83.22 %
  • code
  • 92.79 %
  • assert
  • 97.49 %
  • func
  • 59.38 %
  • line
  • 98.80 %
  • branch
  • 97.99 %
  • cond
  • 93.92 %
  • toggle
  • 87.19 %
  • FSM
  • 86.05 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.730s 196.659us 1 1 100.00
random 1 1 100.00
keymgr_random 6.980s 922.349us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.890s 64.466us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 0.900s 34.679us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 5.310s 192.805us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 5.730s 490.125us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.260s 254.469us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 0.900s 34.679us 1 1 100.00
keymgr_csr_aliasing 5.730s 490.125us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 4.850s 556.074us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.590s 155.619us 1 1 100.00
keymgr_sideload_kmac 3.180s 399.912us 1 1 100.00
keymgr_sideload_aes 13.430s 1310.492us 1 1 100.00
keymgr_sideload_otbn 1.650s 28.646us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 2.340s 211.294us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 3.610s 198.294us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.680s 94.894us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 3.240s 136.966us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 3.580s 497.533us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.690s 129.782us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 7.050s 956.716us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.930s 8.245us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.950s 25.484us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.460s 228.035us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.460s 228.035us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.890s 64.466us 1 1 100.00
keymgr_csr_rw 0.900s 34.679us 1 1 100.00
keymgr_csr_aliasing 5.730s 490.125us 1 1 100.00
keymgr_same_csr_outstanding 1.650s 72.243us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.890s 64.466us 1 1 100.00
keymgr_csr_rw 0.900s 34.679us 1 1 100.00
keymgr_csr_aliasing 5.730s 490.125us 1 1 100.00
keymgr_same_csr_outstanding 1.650s 72.243us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
keymgr_tl_intg_err 7.460s 1108.240us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 2.910s 181.927us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 2.910s 181.927us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 2.910s 181.927us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 2.910s 181.927us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 13.010s 816.790us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 7.460s 1108.240us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 2.910s 181.927us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 4.850s 556.074us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_random 6.980s 922.349us 1 1 100.00
keymgr_csr_rw 0.900s 34.679us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_random 6.980s 922.349us 1 1 100.00
keymgr_csr_rw 0.900s 34.679us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_random 6.980s 922.349us 1 1 100.00
keymgr_csr_rw 0.900s 34.679us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 3.610s 198.294us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.580s 497.533us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 3.580s 497.533us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 6.980s 922.349us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 1.610s 31.301us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 4.340s 544.376us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 3.610s 198.294us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 4.340s 544.376us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 4.340s 544.376us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 4.340s 544.376us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 3.780s 253.198us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 4.340s 544.376us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 3.610s 126.025us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_vseq.sv:1286) [keymgr_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
keymgr_stress_all_with_rand_reset 31037145888918819324240639914543832202373729207056481583143947878403065479790 403
UVM_INFO @ 126024849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---