Simulation Results: kmac/masked

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 82.44 %
  • code
  • 69.76 %
  • assert
  • 97.47 %
  • func
  • 80.08 %
  • line
  • 96.35 %
  • branch
  • 91.05 %
  • cond
  • 86.06 %
  • toggle
  • 29.12 %
  • FSM
  • 46.20 %
Validation stages
V1
100.00%
V2
72.41%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
kmac_smoke 2.500s 235.315us 1 1 100.00
csr_hw_reset 1 1 100.00
kmac_csr_hw_reset 0.920s 133.228us 1 1 100.00
csr_rw 1 1 100.00
kmac_csr_rw 0.890s 115.442us 1 1 100.00
csr_bit_bash 1 1 100.00
kmac_csr_bit_bash 8.910s 1065.193us 1 1 100.00
csr_aliasing 1 1 100.00
kmac_csr_aliasing 4.970s 1616.763us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
kmac_csr_mem_rw_with_rand_reset 1.670s 169.085us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
kmac_csr_rw 0.890s 115.442us 1 1 100.00
kmac_csr_aliasing 4.970s 1616.763us 1 1 100.00
mem_walk 1 1 100.00
kmac_mem_walk 0.770s 14.993us 1 1 100.00
mem_partial_access 1 1 100.00
kmac_mem_partial_access 1.290s 43.645us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg_and_output 1 1 100.00
kmac_long_msg_and_output 2233.010s 32432.465us 1 1 100.00
burst_write 1 1 100.00
kmac_burst_write 197.240s 28229.989us 1 1 100.00
test_vectors 8 8 100.00
kmac_test_vectors_sha3_224 28.670s 2024.972us 1 1 100.00
kmac_test_vectors_sha3_256 35.720s 11162.721us 1 1 100.00
kmac_test_vectors_sha3_384 1066.110s 21211.541us 1 1 100.00
kmac_test_vectors_sha3_512 837.090s 66676.699us 1 1 100.00
kmac_test_vectors_shake_128 160.090s 12427.967us 1 1 100.00
kmac_test_vectors_shake_256 341.860s 70774.495us 1 1 100.00
kmac_test_vectors_kmac 2.060s 130.792us 1 1 100.00
kmac_test_vectors_kmac_xof 1.770s 50.203us 1 1 100.00
sideload 1 1 100.00
kmac_sideload 242.500s 14227.385us 1 1 100.00
app 0 1 0.00
kmac_app 3.240s 268.108us 0 1 0.00
app_with_partial_data 0 1 0.00
kmac_app_with_partial_data 2.930s 87.463us 0 1 0.00
entropy_refresh 0 1 0.00
kmac_entropy_refresh 1.400s 99.884us 0 1 0.00
error 1 1 100.00
kmac_error 19.490s 2131.241us 1 1 100.00
key_error 0 1 0.00
kmac_key_error 0.820s 3.605us 0 1 0.00
sideload_invalid 0 1 0.00
kmac_sideload_invalid 0.780s 3.136us 0 1 0.00
edn_timeout_error 0 1 0.00
kmac_edn_timeout_error 17.650s 404.900us 0 1 0.00
entropy_mode_error 1 1 100.00
kmac_entropy_mode_error 0.880s 21.337us 1 1 100.00
entropy_ready_error 0 1 0.00
kmac_entropy_ready_error 1.080s 170.576us 0 1 0.00
lc_escalation 1 1 100.00
kmac_lc_escalation 1.210s 156.147us 1 1 100.00
stress_all 0 1 0.00
kmac_stress_all 3760.940s 337786.322us 0 1 0.00
intr_test 1 1 100.00
kmac_intr_test 0.710s 64.903us 1 1 100.00
alert_test 1 1 100.00
kmac_alert_test 0.810s 21.051us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
kmac_tl_errors 2.560s 57.518us 1 1 100.00
tl_d_illegal_access 1 1 100.00
kmac_tl_errors 2.560s 57.518us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
kmac_csr_hw_reset 0.920s 133.228us 1 1 100.00
kmac_csr_rw 0.890s 115.442us 1 1 100.00
kmac_csr_aliasing 4.970s 1616.763us 1 1 100.00
kmac_same_csr_outstanding 2.300s 413.143us 1 1 100.00
tl_d_partial_access 4 4 100.00
kmac_csr_hw_reset 0.920s 133.228us 1 1 100.00
kmac_csr_rw 0.890s 115.442us 1 1 100.00
kmac_csr_aliasing 4.970s 1616.763us 1 1 100.00
kmac_same_csr_outstanding 2.300s 413.143us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
kmac_shadow_reg_errors 1.450s 255.552us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
kmac_shadow_reg_errors 1.450s 255.552us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
kmac_shadow_reg_errors 1.450s 255.552us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
kmac_shadow_reg_errors 1.450s 255.552us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
kmac_shadow_reg_errors_with_csr_rw 2.300s 361.823us 1 1 100.00
tl_intg_err 2 2 100.00
kmac_sec_cm 89.490s 41509.393us 1 1 100.00
kmac_tl_intg_err 1.820s 58.192us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
kmac_tl_intg_err 1.820s 58.192us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
kmac_lc_escalation 1.210s 156.147us 1 1 100.00
sec_cm_sw_key_key_masking 1 1 100.00
kmac_smoke 2.500s 235.315us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
kmac_sideload 242.500s 14227.385us 1 1 100.00
sec_cm_cfg_shadowed_config_shadow 1 1 100.00
kmac_shadow_reg_errors 1.450s 255.552us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
kmac_sec_cm 89.490s 41509.393us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
kmac_sec_cm 89.490s 41509.393us 1 1 100.00
sec_cm_packer_ctr_redun 1 1 100.00
kmac_sec_cm 89.490s 41509.393us 1 1 100.00
sec_cm_cfg_shadowed_config_regwen 1 1 100.00
kmac_smoke 2.500s 235.315us 1 1 100.00
sec_cm_fsm_global_esc 1 1 100.00
kmac_lc_escalation 1.210s 156.147us 1 1 100.00
sec_cm_fsm_local_esc 1 1 100.00
kmac_sec_cm 89.490s 41509.393us 1 1 100.00
sec_cm_absorbed_ctrl_mubi 0 1 0.00
kmac_mubi 6.020s 323.273us 0 1 0.00
sec_cm_sw_cmd_ctrl_sparse 1 1 100.00
kmac_smoke 2.500s 235.315us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
kmac_stress_all_with_rand_reset 36.220s 6137.030us 0 1 0.00

Error Messages

   Test seed line log context
Offending '((!$isunknown(rspfifo_rdata)) -> (!$isunknown(tl_o)))' 4 test runs
kmac_sideload_invalid 70821942201638855486151465003592511989806066273218505087992399768164337643038 79
UVM_ERROR @ 3135599 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 3135599 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_key_error 34191443363450382475919836694457615655717115553394360388691737872084805873023 83
UVM_ERROR @ 3604802 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 3604802 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_edn_timeout_error 18301312243292433631938793543245284318225261640768339030319744145941235043022 96
UVM_ERROR @ 404900445 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 404900445 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_ready_error 20109973826594935403337046987509009302442993318158215053380273314549014754 83
UVM_ERROR @ 170575500 ps: (tlul_adapter_sram.sv:684) [ASSERT FAILED] TlOutKnownIfFifoKnown_A
UVM_INFO @ 170575500 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:1671) [scoreboard] Check failed unmasked_digest[i] == dpi_digest[i] (* [*] vs * [*]) Mismatch between unmasked_digest[*] and dpi_digest[*] 4 test runs
kmac_app 34583354636731919714286451366741427030798387576519144771794645831413581383364 84
UVM_INFO @ 268107941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_app_with_partial_data 2519816860828530156781977660830203436528275481526844378420161477188517417959 83
UVM_INFO @ 87462618 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_entropy_refresh 63151341038881014458715363988580475591313489806795682286850708946020444230595 82
UVM_INFO @ 99884346 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all 20687712560749930850916015146368704179228380403343148703989372062641650984283 345
UVM_INFO @ 337786322422 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (kmac_scoreboard.sv:557) [scoreboard] Check failed (kmac_app_rsp.error == app_intf_err) 2 test runs
kmac_mubi 28901569224009953066864667783008227921006166671310913991533892375027970289754 81
UVM_INFO @ 323272964 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
kmac_stress_all_with_rand_reset 14405048308221573257165143919094818609397282374890139187725954790743114130519 201
UVM_INFO @ 6137030486 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---