Simulation Results: lc_ctrl/volatile_unlock_disabled

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 91.17 %
  • code
  • 84.24 %
  • assert
  • 94.97 %
  • func
  • 94.31 %
  • line
  • 97.20 %
  • branch
  • 93.70 %
  • cond
  • 79.86 %
  • toggle
  • 86.87 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 1.600s 43.300us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 1.010s 39.562us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 1.020s 61.479us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 1.820s 590.818us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.630s 41.420us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.960s 125.004us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 1.020s 61.479us 1 1 100.00
lc_ctrl_csr_aliasing 1.630s 41.420us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 5.050s 403.780us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 5.170s 657.963us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.960s 97.900us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 2.180s 96.407us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 8.480s 452.547us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 5.770s 874.218us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 8.480s 452.547us 1 1 100.00
lc_ctrl_prog_failure 2.180s 96.407us 1 1 100.00
lc_ctrl_errors 5.770s 874.218us 1 1 100.00
lc_ctrl_security_escalation 6.300s 279.265us 1 1 100.00
lc_ctrl_jtag_state_failure 68.340s 16644.949us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.880s 317.336us 1 1 100.00
lc_ctrl_jtag_errors 18.450s 1822.616us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 3.000s 241.566us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.810s 906.097us 1 1 100.00
lc_ctrl_jtag_prog_failure 6.880s 317.336us 1 1 100.00
lc_ctrl_jtag_errors 18.450s 1822.616us 1 1 100.00
lc_ctrl_jtag_access 4.280s 4348.505us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 14.120s 3087.641us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.600s 73.834us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.440s 44.410us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 7.450s 408.690us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 2.240s 404.628us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.260s 56.168us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.790s 58.458us 1 1 100.00
lc_ctrl_jtag_alert_test 0.900s 22.893us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 4.180s 814.757us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.990s 18.084us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 138.620s 13526.308us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.750s 13.294us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 1.930s 215.564us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 1.930s 215.564us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.010s 39.562us 1 1 100.00
lc_ctrl_csr_rw 1.020s 61.479us 1 1 100.00
lc_ctrl_csr_aliasing 1.630s 41.420us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 74.127us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 1.010s 39.562us 1 1 100.00
lc_ctrl_csr_rw 1.020s 61.479us 1 1 100.00
lc_ctrl_csr_aliasing 1.630s 41.420us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.020s 74.127us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 5.190s 131.150us 1 1 100.00
lc_ctrl_tl_intg_err 2.110s 1027.417us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 2.110s 1027.417us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 5.170s 657.963us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 8.480s 452.547us 1 1 100.00
lc_ctrl_sec_cm 5.190s 131.150us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 8.480s 452.547us 1 1 100.00
lc_ctrl_sec_cm 5.190s 131.150us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.480s 452.547us 1 1 100.00
lc_ctrl_sec_cm 5.190s 131.150us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 8.480s 452.547us 1 1 100.00
lc_ctrl_sec_cm 5.190s 131.150us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 8.480s 452.547us 1 1 100.00
lc_ctrl_sec_cm 5.190s 131.150us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.480s 452.547us 1 1 100.00
lc_ctrl_sec_cm 5.190s 131.150us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 8.480s 452.547us 1 1 100.00
lc_ctrl_sec_cm 5.190s 131.150us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 8.480s 452.547us 1 1 100.00
lc_ctrl_sec_cm 5.190s 131.150us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 6.300s 279.265us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 5.050s 403.780us 1 1 100.00
lc_ctrl_jtag_state_post_trans 8.810s 906.097us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.300s 502.377us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.300s 502.377us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 4.420s 1244.594us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.170s 312.651us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 4.170s 312.651us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 38.110s 3853.983us 1 1 100.00