Simulation Results: lc_ctrl/volatile_unlock_enabled

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 90.46 %
  • code
  • 83.79 %
  • assert
  • 93.99 %
  • func
  • 93.59 %
  • line
  • 97.00 %
  • branch
  • 93.23 %
  • cond
  • 78.58 %
  • toggle
  • 86.57 %
  • FSM
  • 63.55 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
lc_ctrl_smoke 2.270s 118.511us 1 1 100.00
csr_hw_reset 1 1 100.00
lc_ctrl_csr_hw_reset 0.870s 26.313us 1 1 100.00
csr_rw 1 1 100.00
lc_ctrl_csr_rw 0.930s 26.518us 1 1 100.00
csr_bit_bash 1 1 100.00
lc_ctrl_csr_bit_bash 0.960s 195.188us 1 1 100.00
csr_aliasing 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 23.947us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 0.910s 43.803us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
lc_ctrl_csr_rw 0.930s 26.518us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 23.947us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 1 1 100.00
lc_ctrl_state_post_trans 6.460s 92.934us 1 1 100.00
regwen_during_op 1 1 100.00
lc_ctrl_regwen_during_op 12.050s 404.769us 1 1 100.00
rand_wr_claim_transition_if 1 1 100.00
lc_ctrl_claim_transition_if 0.760s 20.142us 1 1 100.00
lc_prog_failure 1 1 100.00
lc_ctrl_prog_failure 3.980s 1229.280us 1 1 100.00
lc_state_failure 1 1 100.00
lc_ctrl_state_failure 7.580s 2583.307us 1 1 100.00
lc_errors 1 1 100.00
lc_ctrl_errors 7.630s 6916.314us 1 1 100.00
security_escalation 7 7 100.00
lc_ctrl_state_failure 7.580s 2583.307us 1 1 100.00
lc_ctrl_prog_failure 3.980s 1229.280us 1 1 100.00
lc_ctrl_errors 7.630s 6916.314us 1 1 100.00
lc_ctrl_security_escalation 5.510s 6050.368us 1 1 100.00
lc_ctrl_jtag_state_failure 47.760s 4659.031us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.390s 2067.349us 1 1 100.00
lc_ctrl_jtag_errors 19.130s 11187.191us 1 1 100.00
jtag_access 13 13 100.00
lc_ctrl_jtag_smoke 1.860s 884.296us 1 1 100.00
lc_ctrl_jtag_state_post_trans 23.050s 2272.684us 1 1 100.00
lc_ctrl_jtag_prog_failure 5.390s 2067.349us 1 1 100.00
lc_ctrl_jtag_errors 19.130s 11187.191us 1 1 100.00
lc_ctrl_jtag_access 4.920s 1231.163us 1 1 100.00
lc_ctrl_jtag_regwen_during_op 20.530s 7873.061us 1 1 100.00
lc_ctrl_jtag_csr_hw_reset 1.110s 66.197us 1 1 100.00
lc_ctrl_jtag_csr_rw 1.690s 129.205us 1 1 100.00
lc_ctrl_jtag_csr_bit_bash 12.940s 3080.403us 1 1 100.00
lc_ctrl_jtag_csr_aliasing 3.550s 4192.583us 1 1 100.00
lc_ctrl_jtag_same_csr_outstanding 1.180s 174.648us 1 1 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 1.770s 155.484us 1 1 100.00
lc_ctrl_jtag_alert_test 0.760s 104.358us 1 1 100.00
jtag_priority 1 1 100.00
lc_ctrl_jtag_priority 3.330s 442.762us 1 1 100.00
lc_ctrl_volatile_unlock 1 1 100.00
lc_ctrl_volatile_unlock_smoke 0.860s 85.124us 1 1 100.00
stress_all 1 1 100.00
lc_ctrl_stress_all 194.040s 24976.721us 1 1 100.00
alert_test 1 1 100.00
lc_ctrl_alert_test 0.950s 16.657us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
lc_ctrl_tl_errors 4.410s 158.362us 1 1 100.00
tl_d_illegal_access 1 1 100.00
lc_ctrl_tl_errors 4.410s 158.362us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.870s 26.313us 1 1 100.00
lc_ctrl_csr_rw 0.930s 26.518us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 23.947us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.010s 21.409us 1 1 100.00
tl_d_partial_access 4 4 100.00
lc_ctrl_csr_hw_reset 0.870s 26.313us 1 1 100.00
lc_ctrl_csr_rw 0.930s 26.518us 1 1 100.00
lc_ctrl_csr_aliasing 1.130s 23.947us 1 1 100.00
lc_ctrl_same_csr_outstanding 1.010s 21.409us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
lc_ctrl_sec_cm 7.580s 1176.372us 1 1 100.00
lc_ctrl_tl_intg_err 1.760s 164.512us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
lc_ctrl_tl_intg_err 1.760s 164.512us 1 1 100.00
sec_cm_transition_config_regwen 1 1 100.00
lc_ctrl_regwen_during_op 12.050s 404.769us 1 1 100.00
sec_cm_manuf_state_sparse 2 2 100.00
lc_ctrl_state_failure 7.580s 2583.307us 1 1 100.00
lc_ctrl_sec_cm 7.580s 1176.372us 1 1 100.00
sec_cm_transition_ctr_sparse 2 2 100.00
lc_ctrl_state_failure 7.580s 2583.307us 1 1 100.00
lc_ctrl_sec_cm 7.580s 1176.372us 1 1 100.00
sec_cm_manuf_state_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.580s 2583.307us 1 1 100.00
lc_ctrl_sec_cm 7.580s 1176.372us 1 1 100.00
sec_cm_transition_ctr_bkgn_chk 2 2 100.00
lc_ctrl_state_failure 7.580s 2583.307us 1 1 100.00
lc_ctrl_sec_cm 7.580s 1176.372us 1 1 100.00
sec_cm_state_config_sparse 2 2 100.00
lc_ctrl_state_failure 7.580s 2583.307us 1 1 100.00
lc_ctrl_sec_cm 7.580s 1176.372us 1 1 100.00
sec_cm_main_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.580s 2583.307us 1 1 100.00
lc_ctrl_sec_cm 7.580s 1176.372us 1 1 100.00
sec_cm_kmac_fsm_sparse 2 2 100.00
lc_ctrl_state_failure 7.580s 2583.307us 1 1 100.00
lc_ctrl_sec_cm 7.580s 1176.372us 1 1 100.00
sec_cm_main_fsm_local_esc 2 2 100.00
lc_ctrl_state_failure 7.580s 2583.307us 1 1 100.00
lc_ctrl_sec_cm 7.580s 1176.372us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
lc_ctrl_security_escalation 5.510s 6050.368us 1 1 100.00
sec_cm_main_ctrl_flow_consistency 2 2 100.00
lc_ctrl_state_post_trans 6.460s 92.934us 1 1 100.00
lc_ctrl_jtag_state_post_trans 23.050s 2272.684us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.450s 2623.374us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
lc_ctrl_sec_mubi 7.450s 2623.374us 1 1 100.00
sec_cm_token_digest 1 1 100.00
lc_ctrl_sec_token_digest 9.150s 1056.604us 1 1 100.00
sec_cm_token_mux_ctrl_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.010s 416.715us 1 1 100.00
sec_cm_token_valid_mux_redun 1 1 100.00
lc_ctrl_sec_token_mux 5.010s 416.715us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
lc_ctrl_stress_all_with_rand_reset 43.970s 13803.263us 1 1 100.00