Simulation Results: otbn

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 88.83 %
  • code
  • 85.08 %
  • assert
  • 87.78 %
  • func
  • 93.64 %
  • block
  • 99.22 %
  • line
  • 99.42 %
  • branch
  • 94.57 %
  • toggle
  • 82.97 %
  • FSM
  • 63.38 %
Validation stages
V1
100.00%
V2
92.86%
V2S
92.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
otbn_smoke 10.000s 68.401us 1 1 100.00
single_binary 1 1 100.00
otbn_single 6.000s 31.829us 1 1 100.00
csr_hw_reset 1 1 100.00
otbn_csr_hw_reset 27.000s 45.381us 1 1 100.00
csr_rw 1 1 100.00
otbn_csr_rw 27.000s 15.934us 1 1 100.00
csr_bit_bash 1 1 100.00
otbn_csr_bit_bash 30.000s 93.675us 1 1 100.00
csr_aliasing 1 1 100.00
otbn_csr_aliasing 30.000s 14.502us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otbn_csr_mem_rw_with_rand_reset 31.000s 62.693us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otbn_csr_rw 27.000s 15.934us 1 1 100.00
otbn_csr_aliasing 30.000s 14.502us 1 1 100.00
mem_walk 1 1 100.00
otbn_mem_walk 122.000s 11131.420us 1 1 100.00
mem_partial_access 1 1 100.00
otbn_mem_partial_access 25.000s 337.018us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_recovery 1 1 100.00
otbn_reset 37.000s 190.087us 1 1 100.00
multi_error 1 1 100.00
otbn_multi_err 57.000s 255.243us 1 1 100.00
back_to_back 1 1 100.00
otbn_multi 54.000s 759.084us 1 1 100.00
stress_all 0 1 0.00
otbn_stress_all 10.000s 104.700us 0 1 0.00
lc_escalation 1 1 100.00
otbn_escalate 27.000s 21.952us 1 1 100.00
zero_state_err_urnd 1 1 100.00
otbn_zero_state_err_urnd 9.000s 18.372us 1 1 100.00
sw_errs_fatal_chk 1 1 100.00
otbn_sw_errs_fatal_chk 25.000s 97.578us 1 1 100.00
alert_test 1 1 100.00
otbn_alert_test 31.000s 177.725us 1 1 100.00
intr_test 1 1 100.00
otbn_intr_test 24.000s 23.183us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otbn_tl_errors 5.000s 143.996us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otbn_tl_errors 5.000s 143.996us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otbn_csr_hw_reset 27.000s 45.381us 1 1 100.00
otbn_csr_rw 27.000s 15.934us 1 1 100.00
otbn_csr_aliasing 30.000s 14.502us 1 1 100.00
otbn_same_csr_outstanding 3.000s 22.751us 1 1 100.00
tl_d_partial_access 4 4 100.00
otbn_csr_hw_reset 27.000s 45.381us 1 1 100.00
otbn_csr_rw 27.000s 15.934us 1 1 100.00
otbn_csr_aliasing 30.000s 14.502us 1 1 100.00
otbn_same_csr_outstanding 3.000s 22.751us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
mem_integrity 2 2 100.00
otbn_imem_err 29.000s 69.792us 1 1 100.00
otbn_dmem_err 34.000s 37.723us 1 1 100.00
internal_integrity 3 4 75.00
otbn_alu_bignum_mod_err 33.000s 64.086us 1 1 100.00
otbn_controller_ispr_rdata_err 33.000s 265.720us 1 1 100.00
otbn_mac_bignum_acc_err 27.000s 176.023us 0 1 0.00
otbn_urnd_err 7.000s 208.881us 1 1 100.00
illegal_bus_access 1 1 100.00
otbn_illegal_mem_acc 26.000s 51.531us 1 1 100.00
otbn_mem_gnt_acc_err 1 1 100.00
otbn_mem_gnt_acc_err 21.000s 16.690us 1 1 100.00
otbn_non_sec_partial_wipe 1 1 100.00
otbn_partial_wipe 7.000s 24.058us 1 1 100.00
tl_intg_err 1 2 50.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
otbn_tl_intg_err 11.000s 227.383us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
otbn_passthru_mem_tl_intg_err 50.000s 241.694us 1 1 100.00
prim_fsm_check 0 1 0.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
prim_count_check 0 1 0.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
sec_cm_mem_scramble 1 1 100.00
otbn_smoke 10.000s 68.401us 1 1 100.00
sec_cm_data_mem_integrity 1 1 100.00
otbn_dmem_err 34.000s 37.723us 1 1 100.00
sec_cm_instruction_mem_integrity 1 1 100.00
otbn_imem_err 29.000s 69.792us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otbn_tl_intg_err 11.000s 227.383us 1 1 100.00
sec_cm_controller_fsm_global_esc 1 1 100.00
otbn_escalate 27.000s 21.952us 1 1 100.00
sec_cm_controller_fsm_local_esc 4 5 80.00
otbn_imem_err 29.000s 69.792us 1 1 100.00
otbn_dmem_err 34.000s 37.723us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 18.372us 1 1 100.00
otbn_illegal_mem_acc 26.000s 51.531us 1 1 100.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
sec_cm_controller_fsm_sparse 0 1 0.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
sec_cm_scramble_key_sideload 1 1 100.00
otbn_single 6.000s 31.829us 1 1 100.00
sec_cm_scramble_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 29.000s 69.792us 1 1 100.00
otbn_dmem_err 34.000s 37.723us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 18.372us 1 1 100.00
otbn_illegal_mem_acc 26.000s 51.531us 1 1 100.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
sec_cm_scramble_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_global_esc 1 1 100.00
otbn_escalate 27.000s 21.952us 1 1 100.00
sec_cm_start_stop_ctrl_fsm_local_esc 4 5 80.00
otbn_imem_err 29.000s 69.792us 1 1 100.00
otbn_dmem_err 34.000s 37.723us 1 1 100.00
otbn_zero_state_err_urnd 9.000s 18.372us 1 1 100.00
otbn_illegal_mem_acc 26.000s 51.531us 1 1 100.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
sec_cm_start_stop_ctrl_fsm_sparse 0 1 0.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
sec_cm_data_reg_sw_sca 1 1 100.00
otbn_single 6.000s 31.829us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
otbn_ctrl_redun 28.000s 60.037us 1 1 100.00
sec_cm_pc_ctrl_flow_redun 1 1 100.00
otbn_pc_ctrl_flow_redun 7.000s 52.570us 1 1 100.00
sec_cm_rnd_bus_consistency 1 1 100.00
otbn_rnd_sec_cm 39.000s 243.408us 1 1 100.00
sec_cm_rnd_rng_digest 1 1 100.00
otbn_rnd_sec_cm 39.000s 243.408us 1 1 100.00
sec_cm_rf_base_data_reg_sw_integrity 1 1 100.00
otbn_rf_base_intg_err 9.000s 62.847us 1 1 100.00
sec_cm_rf_base_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
sec_cm_stack_wr_ptr_ctr_redun 0 1 0.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
sec_cm_rf_bignum_data_reg_sw_integrity 1 1 100.00
otbn_rf_bignum_intg_err 9.000s 57.505us 1 1 100.00
sec_cm_rf_bignum_data_reg_sw_glitch_detect 0 1 0.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
sec_cm_loop_stack_ctr_redun 0 1 0.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
sec_cm_loop_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 28.000s 154.401us 1 1 100.00
sec_cm_call_stack_addr_integrity 1 1 100.00
otbn_stack_addr_integ_chk 28.000s 154.401us 1 1 100.00
sec_cm_start_stop_ctrl_state_consistency 1 1 100.00
otbn_sec_wipe_err 6.000s 10.206us 1 1 100.00
sec_cm_data_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 31.829us 1 1 100.00
sec_cm_instruction_mem_sec_wipe 1 1 100.00
otbn_single 6.000s 31.829us 1 1 100.00
sec_cm_data_reg_sw_sec_wipe 1 1 100.00
otbn_single 6.000s 31.829us 1 1 100.00
sec_cm_write_mem_integrity 1 1 100.00
otbn_multi 54.000s 759.084us 1 1 100.00
sec_cm_ctrl_flow_count 1 1 100.00
otbn_single 6.000s 31.829us 1 1 100.00
sec_cm_ctrl_flow_sca 1 1 100.00
otbn_single 6.000s 31.829us 1 1 100.00
sec_cm_data_mem_sw_noaccess 1 1 100.00
otbn_sw_no_acc 5.000s 39.320us 1 1 100.00
sec_cm_key_sideload 1 1 100.00
otbn_single 6.000s 31.829us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 0 1 0.00
otbn_sec_cm 20.000s 70.259us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
otbn_stress_all_with_rand_reset 35.000s 202.713us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
otbn_smoke_vectorized 7.000s 70.321us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (cip_base_scoreboard.sv:255) scoreboard [scoreboard] alert fatal has unexpected timeout error 2 test runs
otbn_mac_bignum_acc_err 83425639598074929471979823675939883543673043144865121813460049312981551053830 118
UVM_INFO @ 176023088 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otbn_stress_all 18323310367694677600233890064193838132679927199119545614371296609749114166576 163
UVM_INFO @ 104700276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1287) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
otbn_stress_all_with_rand_reset 89341798642996017027302094902584663277052912378199689072977112174009578991313 154
UVM_INFO @ 202713450 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
xmsim: *E,ASRTST (/nightly/current_run/scratch/master/otbn-sim-xcelium/default/fusesoc-work/src/lowrisc_prim_fifo_*/rtl/prim_fifo_sync.sv,224): Assertion DataKnown_A has failed 1 test run
otbn_sec_cm 30521297108672895238136858237469406738142781039970605675996373654582331472863 141
UVM_ERROR @ 70259297 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
UVM_INFO @ 70259297 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---