Simulation Results: otp_ctrl

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 81.95 %
  • code
  • 78.88 %
  • assert
  • 94.57 %
  • func
  • 72.40 %
  • line
  • 88.50 %
  • branch
  • 83.22 %
  • cond
  • 90.32 %
  • toggle
  • 89.14 %
  • FSM
  • 43.23 %
Validation stages
V1
100.00%
V2
90.00%
V2S
77.78%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
otp_ctrl_wake_up 1.610s 129.324us 1 1 100.00
smoke 1 1 100.00
otp_ctrl_smoke 8.530s 4155.308us 1 1 100.00
csr_hw_reset 1 1 100.00
otp_ctrl_csr_hw_reset 1.470s 264.037us 1 1 100.00
csr_rw 1 1 100.00
otp_ctrl_csr_rw 1.330s 87.620us 1 1 100.00
csr_bit_bash 1 1 100.00
otp_ctrl_csr_bit_bash 4.370s 282.721us 1 1 100.00
csr_aliasing 1 1 100.00
otp_ctrl_csr_aliasing 3.290s 151.919us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
otp_ctrl_csr_mem_rw_with_rand_reset 1.520s 75.665us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
otp_ctrl_csr_rw 1.330s 87.620us 1 1 100.00
otp_ctrl_csr_aliasing 3.290s 151.919us 1 1 100.00
mem_walk 1 1 100.00
otp_ctrl_mem_walk 1.160s 74.475us 1 1 100.00
mem_partial_access 1 1 100.00
otp_ctrl_mem_partial_access 1.150s 41.900us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
dai_access_partition_walk 1 1 100.00
otp_ctrl_partition_walk 14.670s 813.702us 1 1 100.00
init_fail 1 1 100.00
otp_ctrl_init_fail 2.740s 189.913us 1 1 100.00
partition_check 1 2 50.00
otp_ctrl_background_chks 4.130s 698.472us 1 1 100.00
otp_ctrl_check_fail 2.200s 214.721us 0 1 0.00
regwen_during_otp_init 1 1 100.00
otp_ctrl_regwen 2.940s 491.416us 1 1 100.00
partition_lock 1 1 100.00
otp_ctrl_dai_lock 8.550s 5802.527us 1 1 100.00
interface_key_check 1 1 100.00
otp_ctrl_parallel_key_req 20.550s 9878.199us 1 1 100.00
lc_interactions 2 2 100.00
otp_ctrl_parallel_lc_req 11.420s 1101.919us 1 1 100.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
otp_dai_errors 1 1 100.00
otp_ctrl_dai_errs 14.670s 1001.347us 1 1 100.00
otp_macro_errors 0 1 0.00
otp_ctrl_macro_errs 5.410s 384.033us 0 1 0.00
test_access 1 1 100.00
otp_ctrl_test_access 25.740s 8904.197us 1 1 100.00
stress_all 1 1 100.00
otp_ctrl_stress_all 133.310s 111164.537us 1 1 100.00
intr_test 1 1 100.00
otp_ctrl_intr_test 1.100s 40.504us 1 1 100.00
alert_test 1 1 100.00
otp_ctrl_alert_test 1.520s 110.131us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
otp_ctrl_tl_errors 3.600s 82.911us 1 1 100.00
tl_d_illegal_access 1 1 100.00
otp_ctrl_tl_errors 3.600s 82.911us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.470s 264.037us 1 1 100.00
otp_ctrl_csr_rw 1.330s 87.620us 1 1 100.00
otp_ctrl_csr_aliasing 3.290s 151.919us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.260s 1122.038us 1 1 100.00
tl_d_partial_access 4 4 100.00
otp_ctrl_csr_hw_reset 1.470s 264.037us 1 1 100.00
otp_ctrl_csr_rw 1.330s 87.620us 1 1 100.00
otp_ctrl_csr_aliasing 3.290s 151.919us 1 1 100.00
otp_ctrl_same_csr_outstanding 2.260s 1122.038us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
tl_intg_err 2 2 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
otp_ctrl_tl_intg_err 11.850s 19803.355us 1 1 100.00
prim_count_check 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
prim_fsm_check 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
otp_ctrl_tl_intg_err 11.850s 19803.355us 1 1 100.00
sec_cm_secret_mem_scramble 1 1 100.00
otp_ctrl_smoke 8.530s 4155.308us 1 1 100.00
sec_cm_part_mem_digest 1 1 100.00
otp_ctrl_smoke 8.530s 4155.308us 1 1 100.00
sec_cm_dai_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_kdi_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_lci_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_part_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_scrmbl_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_timer_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_dai_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_kdi_seed_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_kdi_entropy_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_lci_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_part_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_scrmbl_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_timer_integ_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_timer_cnsty_ctr_redun 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_timer_lfsr_redun 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_dai_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_lci_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
sec_cm_kdi_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
sec_cm_part_fsm_local_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
otp_ctrl_macro_errs 5.410s 384.033us 0 1 0.00
sec_cm_scrmbl_fsm_local_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
sec_cm_timer_fsm_local_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_dai_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_lci_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
sec_cm_kdi_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
sec_cm_part_fsm_global_esc 1 2 50.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
otp_ctrl_macro_errs 5.410s 384.033us 0 1 0.00
sec_cm_scrmbl_fsm_global_esc 1 1 100.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
sec_cm_timer_fsm_global_esc 2 2 100.00
otp_ctrl_parallel_lc_esc 4.520s 206.714us 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_part_data_reg_integrity 1 1 100.00
otp_ctrl_init_fail 2.740s 189.913us 1 1 100.00
sec_cm_part_data_reg_bkgn_chk 0 1 0.00
otp_ctrl_check_fail 2.200s 214.721us 0 1 0.00
sec_cm_part_mem_regren 1 1 100.00
otp_ctrl_dai_lock 8.550s 5802.527us 1 1 100.00
sec_cm_part_mem_sw_unreadable 1 1 100.00
otp_ctrl_dai_lock 8.550s 5802.527us 1 1 100.00
sec_cm_part_mem_sw_unwritable 1 1 100.00
otp_ctrl_dai_lock 8.550s 5802.527us 1 1 100.00
sec_cm_lc_part_mem_sw_noaccess 1 1 100.00
otp_ctrl_dai_lock 8.550s 5802.527us 1 1 100.00
sec_cm_access_ctrl_mubi 1 1 100.00
otp_ctrl_dai_lock 8.550s 5802.527us 1 1 100.00
sec_cm_token_valid_ctrl_mubi 1 1 100.00
otp_ctrl_smoke 8.530s 4155.308us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
otp_ctrl_dai_lock 8.550s 5802.527us 1 1 100.00
sec_cm_test_bus_lc_gated 1 1 100.00
otp_ctrl_smoke 8.530s 4155.308us 1 1 100.00
sec_cm_test_tl_lc_gate_fsm_sparse 1 1 100.00
otp_ctrl_sec_cm 114.700s 21640.236us 1 1 100.00
sec_cm_direct_access_config_regwen 1 1 100.00
otp_ctrl_regwen 2.940s 491.416us 1 1 100.00
sec_cm_check_trigger_config_regwen 1 1 100.00
otp_ctrl_smoke 8.530s 4155.308us 1 1 100.00
sec_cm_check_config_regwen 1 1 100.00
otp_ctrl_smoke 8.530s 4155.308us 1 1 100.00
sec_cm_macro_mem_integrity 0 1 0.00
otp_ctrl_macro_errs 5.410s 384.033us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
otp_ctrl_low_freq_read 1 1 100.00
otp_ctrl_low_freq_read 9.160s 3572.985us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
otp_ctrl_stress_all_with_rand_reset 16.590s 4787.706us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (otp_ctrl_scoreboard.sv:1202) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) reg name: otp_ctrl_core_reg_block.direct_access_rdata_* 2 test runs
otp_ctrl_check_fail 108289686630530596174606774539288663067556551115543421190460443570031175135980 1723
UVM_INFO @ 214721018 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
otp_ctrl_macro_errs 113827763749079771711940667897821920145805210162126024903431031309585119641894 2435
UVM_INFO @ 384032838 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (otp_ctrl_scoreboard.sv:1825) [scoreboard] Check failed item.d_data == exp_data (* [*] vs * [*]) d_data mismatch when d_error = * 1 test run
otp_ctrl_stress_all_with_rand_reset 80105029051650022799457878623302492886249585292940920051370158066473069086181 1125
UVM_INFO @ 4787705830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---