Simulation Results: pwrmgr

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.11 %
  • code
  • 97.34 %
  • assert
  • 98.96 %
  • func
  • 98.02 %
  • line
  • 99.09 %
  • branch
  • 96.37 %
  • cond
  • 95.62 %
  • toggle
  • 99.62 %
  • FSM
  • 96.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.680s 24.392us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.640s 32.702us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.720s 50.067us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.630s 683.440us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 1.010s 192.556us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.790s 46.156us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.720s 50.067us 1 1 100.00
pwrmgr_csr_aliasing 1.010s 192.556us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.920s 340.291us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.920s 340.291us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.750s 83.612us 1 1 100.00
pwrmgr_lowpower_invalid 0.780s 44.545us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.650s 62.461us 1 1 100.00
pwrmgr_reset_invalid 0.750s 485.573us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.650s 62.461us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.640s 95.535us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.660s 43.347us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.980s 80.537us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 1.820s 1048.703us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.640s 29.368us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.450s 69.888us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.450s 69.888us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.640s 32.702us 1 1 100.00
pwrmgr_csr_rw 0.720s 50.067us 1 1 100.00
pwrmgr_csr_aliasing 1.010s 192.556us 1 1 100.00
pwrmgr_same_csr_outstanding 0.670s 103.896us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.640s 32.702us 1 1 100.00
pwrmgr_csr_rw 0.720s 50.067us 1 1 100.00
pwrmgr_csr_aliasing 1.010s 192.556us 1 1 100.00
pwrmgr_same_csr_outstanding 0.670s 103.896us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pwrmgr_tl_intg_err 1.020s 143.883us 1 1 100.00
pwrmgr_sec_cm 1.750s 647.343us 1 1 100.00
prim_count_check 1 1 100.00
pwrmgr_sec_cm 1.750s 647.343us 1 1 100.00
prim_fsm_check 1 1 100.00
pwrmgr_sec_cm 1.750s 647.343us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pwrmgr_tl_intg_err 1.020s 143.883us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.890s 1001.110us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 2 2 100.00
pwrmgr_wakeup_reset 0.640s 95.535us 1 1 100.00
pwrmgr_repeat_wakeup_reset 1.490s 970.844us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.710s 58.988us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.690s 30.522us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 1 1 100.00
pwrmgr_sec_cm 1.750s 647.343us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
pwrmgr_sec_cm 1.750s 647.343us 1 1 100.00
sec_cm_fsm_terminal 1 1 100.00
pwrmgr_sec_cm 1.750s 647.343us 1 1 100.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.650s 94.109us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.620s 49.034us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.680s 101.771us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.720s 50.067us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.720s 50.067us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 1 1 100.00
pwrmgr_escalation_timeout 0.720s 257.968us 1 1 100.00
stress_all_with_rand_reset 0 1 0.00
pwrmgr_stress_all_with_rand_reset 2.010s 11335.378us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (pwrmgr_reset_vseq.sv:62) [pwrmgr_reset_vseq] wait timeout occurred! 1 test run
pwrmgr_stress_all_with_rand_reset 84986663640042839110642754865710356322131412934500630895834202653122582298450 271
UVM_INFO @ 11335378170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---