Simulation Results: rom_ctrl/64kb

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 96.13 %
  • code
  • 94.43 %
  • assert
  • 96.81 %
  • func
  • 97.14 %
  • line
  • 99.33 %
  • branch
  • 98.91 %
  • cond
  • 98.37 %
  • toggle
  • 95.54 %
  • FSM
  • 80.00 %
Validation stages
V1
100.00%
V2
88.89%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rom_ctrl_smoke 7.640s 857.343us 1 1 100.00
csr_hw_reset 1 1 100.00
rom_ctrl_csr_hw_reset 8.440s 1171.981us 1 1 100.00
csr_rw 1 1 100.00
rom_ctrl_csr_rw 6.460s 1030.038us 1 1 100.00
csr_bit_bash 1 1 100.00
rom_ctrl_csr_bit_bash 5.890s 370.827us 1 1 100.00
csr_aliasing 1 1 100.00
rom_ctrl_csr_aliasing 7.150s 287.081us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.020s 2065.786us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rom_ctrl_csr_rw 6.460s 1030.038us 1 1 100.00
rom_ctrl_csr_aliasing 7.150s 287.081us 1 1 100.00
mem_walk 1 1 100.00
rom_ctrl_mem_walk 6.640s 1030.698us 1 1 100.00
mem_partial_access 1 1 100.00
rom_ctrl_mem_partial_access 6.660s 219.971us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 0 1 0.00
rom_ctrl_max_throughput_chk 6.130s 189.570us 0 1 0.00
stress_all 1 1 100.00
rom_ctrl_stress_all 19.070s 575.800us 1 1 100.00
kmac_err_chk 1 1 100.00
rom_ctrl_kmac_err_chk 13.860s 2107.812us 1 1 100.00
alert_test 1 1 100.00
rom_ctrl_alert_test 7.290s 294.498us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rom_ctrl_tl_errors 8.640s 293.328us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rom_ctrl_tl_errors 8.640s 293.328us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.440s 1171.981us 1 1 100.00
rom_ctrl_csr_rw 6.460s 1030.038us 1 1 100.00
rom_ctrl_csr_aliasing 7.150s 287.081us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.130s 567.025us 1 1 100.00
tl_d_partial_access 4 4 100.00
rom_ctrl_csr_hw_reset 8.440s 1171.981us 1 1 100.00
rom_ctrl_csr_rw 6.460s 1030.038us 1 1 100.00
rom_ctrl_csr_aliasing 7.150s 287.081us 1 1 100.00
rom_ctrl_same_csr_outstanding 7.130s 567.025us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.530s 25114.449us 1 1 100.00
passthru_mem_tl_intg_err 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.800s 1118.919us 1 1 100.00
tl_intg_err 2 2 100.00
rom_ctrl_sec_cm 451.940s 606.904us 1 1 100.00
rom_ctrl_tl_intg_err 98.820s 2225.399us 1 1 100.00
prim_fsm_check 1 1 100.00
rom_ctrl_sec_cm 451.940s 606.904us 1 1 100.00
prim_count_check 1 1 100.00
rom_ctrl_sec_cm 451.940s 606.904us 1 1 100.00
sec_cm_checker_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.530s 25114.449us 1 1 100.00
sec_cm_checker_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.530s 25114.449us 1 1 100.00
sec_cm_checker_fsm_local_esc 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.530s 25114.449us 1 1 100.00
sec_cm_compare_ctrl_flow_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.530s 25114.449us 1 1 100.00
sec_cm_compare_ctr_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.530s 25114.449us 1 1 100.00
sec_cm_compare_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 451.940s 606.904us 1 1 100.00
sec_cm_fsm_sparse 1 1 100.00
rom_ctrl_sec_cm 451.940s 606.904us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
rom_ctrl_smoke 7.640s 857.343us 1 1 100.00
sec_cm_mem_digest 1 1 100.00
rom_ctrl_smoke 7.640s 857.343us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
rom_ctrl_smoke 7.640s 857.343us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rom_ctrl_tl_intg_err 98.820s 2225.399us 1 1 100.00
sec_cm_bus_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.530s 25114.449us 1 1 100.00
rom_ctrl_kmac_err_chk 13.860s 2107.812us 1 1 100.00
sec_cm_mux_mubi 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.530s 25114.449us 1 1 100.00
sec_cm_mux_consistency 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.530s 25114.449us 1 1 100.00
sec_cm_ctrl_redun 1 1 100.00
rom_ctrl_corrupt_sig_fatal_chk 88.530s 25114.449us 1 1 100.00
sec_cm_ctrl_mem_integrity 1 1 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.800s 1118.919us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
rom_ctrl_sec_cm 451.940s 606.904us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
rom_ctrl_stress_all_with_rand_reset 72.060s 4948.236us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (rom_ctrl_throughput_vseq.sv:52) [rom_ctrl_throughput_vseq] Check failed num_cycles == num_mem_reads + * (* [*] vs * [*]) 1 test run
rom_ctrl_max_throughput_chk 14591820210970344970535879829489160793876075676785375189631321020753959607593 79
UVM_INFO @ 189569583 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---