Simulation Results: rstmgr

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 98.77 %
  • code
  • 99.16 %
  • assert
  • 98.66 %
  • func
  • 98.51 %
  • line
  • 99.51 %
  • branch
  • 99.83 %
  • cond
  • 98.12 %
  • toggle
  • 99.16 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.380s 290.372us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.870s 126.772us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.110s 90.448us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 2.980s 376.081us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.550s 220.109us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.840s 121.774us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.110s 90.448us 1 1 100.00
rstmgr_csr_aliasing 1.550s 220.109us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.740s 110.323us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.430s 144.523us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.320s 321.695us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.100s 915.835us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.100s 915.835us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.100s 915.835us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.100s 915.835us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 36.710s 16678.632us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.890s 95.500us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.730s 313.193us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.730s 313.193us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.870s 126.772us 1 1 100.00
rstmgr_csr_rw 1.110s 90.448us 1 1 100.00
rstmgr_csr_aliasing 1.550s 220.109us 1 1 100.00
rstmgr_same_csr_outstanding 1.030s 111.991us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.870s 126.772us 1 1 100.00
rstmgr_csr_rw 1.110s 90.448us 1 1 100.00
rstmgr_csr_aliasing 1.550s 220.109us 1 1 100.00
rstmgr_same_csr_outstanding 1.030s 111.991us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 22.470s 16819.200us 1 1 100.00
rstmgr_tl_intg_err 2.310s 974.945us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 22.470s 16819.200us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 22.470s 16819.200us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.310s 974.945us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.070s 178.490us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 4.540s 1407.918us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.010s 302.362us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 22.470s 16819.200us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.110s 90.448us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.110s 90.448us 1 1 100.00