Simulation Results: rv_timer

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 97.67 %
  • code
  • 100.00 %
  • assert
  • 96.82 %
  • func
  • 96.18 %
  • line
  • 100.00 %
  • branch
  • 100.00 %
  • cond
  • 100.00 %
  • toggle
  • 100.00 %
Validation stages
V1
100.00%
V2
90.91%
V2S
100.00%
V3
33.33%
Testpoint Test Max Runtime Sim Time Pass Total %
random 1 1 100.00
rv_timer_random 1.220s 1264.375us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_timer_csr_hw_reset 0.580s 32.355us 1 1 100.00
csr_rw 1 1 100.00
rv_timer_csr_rw 0.560s 58.212us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_timer_csr_bit_bash 2.110s 606.321us 1 1 100.00
csr_aliasing 1 1 100.00
rv_timer_csr_aliasing 0.730s 68.472us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rv_timer_csr_mem_rw_with_rand_reset 0.770s 20.901us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_timer_csr_rw 0.560s 58.212us 1 1 100.00
rv_timer_csr_aliasing 0.730s 68.472us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
random_reset 0 1 0.00
rv_timer_random_reset 0.650s 337.108us 0 1 0.00
disabled 1 1 100.00
rv_timer_disabled 1.970s 1962.789us 1 1 100.00
cfg_update_on_fly 1 1 100.00
rv_timer_cfg_update_on_fly 286.200s 368027.017us 1 1 100.00
no_interrupt_test 1 1 100.00
rv_timer_cfg_update_on_fly 286.200s 368027.017us 1 1 100.00
stress 1 1 100.00
rv_timer_stress_all 2.260s 6935.159us 1 1 100.00
alert_test 1 1 100.00
rv_timer_alert_test 0.570s 13.663us 1 1 100.00
intr_test 1 1 100.00
rv_timer_intr_test 0.590s 37.698us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rv_timer_tl_errors 1.550s 89.270us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rv_timer_tl_errors 1.550s 89.270us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rv_timer_csr_hw_reset 0.580s 32.355us 1 1 100.00
rv_timer_csr_rw 0.560s 58.212us 1 1 100.00
rv_timer_csr_aliasing 0.730s 68.472us 1 1 100.00
rv_timer_same_csr_outstanding 0.600s 52.182us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_timer_csr_hw_reset 0.580s 32.355us 1 1 100.00
rv_timer_csr_rw 0.560s 58.212us 1 1 100.00
rv_timer_csr_aliasing 0.730s 68.472us 1 1 100.00
rv_timer_same_csr_outstanding 0.600s 52.182us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_timer_sec_cm 1.010s 1863.730us 1 1 100.00
rv_timer_tl_intg_err 1.050s 104.738us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_timer_tl_intg_err 1.050s 104.738us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
min_value 0 1 0.00
rv_timer_min 5.090s 1561.378us 0 1 0.00
max_value 0 1 0.00
rv_timer_max 1.230s 264.183us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
rv_timer_stress_all_with_rand_reset 51.340s 13243.254us 1 1 100.00

Error Messages

   Test seed line log context
UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * 2 test runs
rv_timer_min 33618525457142140328839829351700577421474246383158888290792801443606997267297 77
UVM_INFO @ 1561377506 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
rv_timer_random_reset 115649792395506662313078195934653856909424050134162673113292970925534976056664 75
UVM_INFO @ 337107589 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (rv_timer_scoreboard.sv:231) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) 1 test run
rv_timer_max 49443614669104377844850051036055027736238470878192430851980189764755430791328 80
UVM_INFO @ 264182714 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---