Simulation Results: spi_host

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 92.11 %
  • code
  • 91.30 %
  • assert
  • 96.79 %
  • func
  • 88.24 %
  • block
  • 96.96 %
  • line
  • 98.76 %
  • branch
  • 93.35 %
  • toggle
  • 73.07 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
spi_host_smoke 6.000s 3617.358us 1 1 100.00
csr_hw_reset 1 1 100.00
spi_host_csr_hw_reset 1.000s 100.100us 1 1 100.00
csr_rw 1 1 100.00
spi_host_csr_rw 1.000s 28.997us 1 1 100.00
csr_bit_bash 1 1 100.00
spi_host_csr_bit_bash 2.000s 147.467us 1 1 100.00
csr_aliasing 1 1 100.00
spi_host_csr_aliasing 1.000s 16.269us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
spi_host_csr_mem_rw_with_rand_reset 2.000s 29.938us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
spi_host_csr_rw 1.000s 28.997us 1 1 100.00
spi_host_csr_aliasing 1.000s 16.269us 1 1 100.00
mem_walk 1 1 100.00
spi_host_mem_walk 1.000s 16.696us 1 1 100.00
mem_partial_access 1 1 100.00
spi_host_mem_partial_access 1.000s 16.404us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
performance 1 1 100.00
spi_host_performance 1.000s 21.702us 1 1 100.00
error_event_intr 3 3 100.00
spi_host_overflow_underflow 3.000s 76.357us 1 1 100.00
spi_host_error_cmd 1.000s 159.225us 1 1 100.00
spi_host_event 30.000s 5784.247us 1 1 100.00
clock_rate 1 1 100.00
spi_host_speed 1.000s 19.547us 1 1 100.00
speed 1 1 100.00
spi_host_speed 1.000s 19.547us 1 1 100.00
chip_select_timing 1 1 100.00
spi_host_speed 1.000s 19.547us 1 1 100.00
upper_range_clkdiv 1 1 100.00
spi_host_upper_range_clkdiv 207.000s 8250.940us 1 1 100.00
sw_reset 1 1 100.00
spi_host_sw_reset 7.000s 401.082us 1 1 100.00
passthrough_mode 1 1 100.00
spi_host_passthrough_mode 1.000s 60.144us 1 1 100.00
cpol_cpha 1 1 100.00
spi_host_speed 1.000s 19.547us 1 1 100.00
full_cycle 1 1 100.00
spi_host_speed 1.000s 19.547us 1 1 100.00
duplex 1 1 100.00
spi_host_smoke 6.000s 3617.358us 1 1 100.00
tx_rx_only 1 1 100.00
spi_host_smoke 6.000s 3617.358us 1 1 100.00
stress_all 1 1 100.00
spi_host_stress_all 13.000s 2746.997us 1 1 100.00
spien 1 1 100.00
spi_host_spien 5.000s 1440.216us 1 1 100.00
stall 1 1 100.00
spi_host_status_stall 76.000s 31394.757us 1 1 100.00
Idlecsbactive 1 1 100.00
spi_host_idlecsbactive 2.000s 190.021us 1 1 100.00
data_fifo_status 1 1 100.00
spi_host_overflow_underflow 3.000s 76.357us 1 1 100.00
alert_test 1 1 100.00
spi_host_alert_test 1.000s 18.639us 1 1 100.00
intr_test 1 1 100.00
spi_host_intr_test 1.000s 150.003us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
spi_host_tl_errors 1.000s 25.535us 1 1 100.00
tl_d_illegal_access 1 1 100.00
spi_host_tl_errors 1.000s 25.535us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 100.100us 1 1 100.00
spi_host_csr_rw 1.000s 28.997us 1 1 100.00
spi_host_csr_aliasing 1.000s 16.269us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 27.097us 1 1 100.00
tl_d_partial_access 4 4 100.00
spi_host_csr_hw_reset 1.000s 100.100us 1 1 100.00
spi_host_csr_rw 1.000s 28.997us 1 1 100.00
spi_host_csr_aliasing 1.000s 16.269us 1 1 100.00
spi_host_same_csr_outstanding 1.000s 27.097us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
spi_host_tl_intg_err 2.000s 214.195us 1 1 100.00
spi_host_sec_cm 2.000s 224.544us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
spi_host_tl_intg_err 2.000s 214.195us 1 1 100.00