Simulation Results: sram_ctrl/main

 
08/07/2026 15:30:33 DVSim: v1.49.12 sha: dba823a json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 95.40 %
  • code
  • 94.93 %
  • assert
  • 97.28 %
  • func
  • 94.00 %
  • block
  • 95.03 %
  • line
  • 95.65 %
  • branch
  • 92.23 %
  • toggle
  • 91.84 %
  • FSM
  • 100.00 %
Validation stages
V1
100.00%
V2
85.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sram_ctrl_smoke 3.000s 550.655us 1 1 100.00
csr_hw_reset 1 1 100.00
sram_ctrl_csr_hw_reset 1.000s 21.603us 1 1 100.00
csr_rw 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.261us 1 1 100.00
csr_bit_bash 1 1 100.00
sram_ctrl_csr_bit_bash 2.000s 174.764us 1 1 100.00
csr_aliasing 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 32.518us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.000s 346.245us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sram_ctrl_csr_rw 1.000s 25.261us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 32.518us 1 1 100.00
mem_walk 1 1 100.00
sram_ctrl_mem_walk 113.000s 22253.993us 1 1 100.00
mem_partial_access 1 1 100.00
sram_ctrl_mem_partial_access 37.000s 1677.701us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 1 1 100.00
sram_ctrl_multiple_keys 16.000s 9940.707us 1 1 100.00
stress_pipeline 1 1 100.00
sram_ctrl_stress_pipeline 138.000s 4084.695us 1 1 100.00
bijection 1 1 100.00
sram_ctrl_bijection 158.000s 18222.746us 1 1 100.00
access_during_key_req 1 1 100.00
sram_ctrl_access_during_key_req 38.000s 38417.338us 1 1 100.00
lc_escalation 1 1 100.00
sram_ctrl_lc_escalation 34.000s 34351.460us 1 1 100.00
executable 1 1 100.00
sram_ctrl_executable 24.000s 23196.186us 1 1 100.00
partial_access 2 2 100.00
sram_ctrl_partial_access 3.000s 3972.599us 1 1 100.00
sram_ctrl_partial_access_b2b 255.000s 309201.394us 1 1 100.00
max_throughput 0 3 0.00
sram_ctrl_max_throughput 4.000s 3301.704us 0 1 0.00
sram_ctrl_throughput_w_partial_write 5.000s 2641.899us 0 1 0.00
sram_ctrl_throughput_w_readback 4.000s 2077.034us 0 1 0.00
regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1120.220us 1 1 100.00
ram_cfg 1 1 100.00
sram_ctrl_ram_cfg 2.000s 1423.823us 1 1 100.00
stress_all 1 1 100.00
sram_ctrl_stress_all 125.000s 69053.442us 1 1 100.00
alert_test 1 1 100.00
sram_ctrl_alert_test 1.000s 24.511us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 150.016us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sram_ctrl_tl_errors 4.000s 150.016us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 21.603us 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.261us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 32.518us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 217.830us 1 1 100.00
tl_d_partial_access 4 4 100.00
sram_ctrl_csr_hw_reset 1.000s 21.603us 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.261us 1 1 100.00
sram_ctrl_csr_aliasing 1.000s 32.518us 1 1 100.00
sram_ctrl_same_csr_outstanding 2.000s 217.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 7055.161us 1 1 100.00
tl_intg_err 2 2 100.00
sram_ctrl_sec_cm 2.000s 1613.614us 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 363.470us 1 1 100.00
prim_count_check 1 1 100.00
sram_ctrl_sec_cm 2.000s 1613.614us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sram_ctrl_tl_intg_err 2.000s 363.470us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1120.220us 1 1 100.00
sec_cm_readback_config_regwen 1 1 100.00
sram_ctrl_regwen 12.000s 1120.220us 1 1 100.00
sec_cm_exec_config_regwen 1 1 100.00
sram_ctrl_csr_rw 1.000s 25.261us 1 1 100.00
sec_cm_exec_config_mubi 1 1 100.00
sram_ctrl_executable 24.000s 23196.186us 1 1 100.00
sec_cm_exec_intersig_mubi 1 1 100.00
sram_ctrl_executable 24.000s 23196.186us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 1 1 100.00
sram_ctrl_executable 24.000s 23196.186us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
sram_ctrl_lc_escalation 34.000s 34351.460us 1 1 100.00
sec_cm_prim_ram_ctrl_mubi 1 1 100.00
sram_ctrl_mubi_enc_err 3.000s 691.658us 1 1 100.00
sec_cm_mem_integrity 1 1 100.00
sram_ctrl_passthru_mem_tl_intg_err 20.000s 7055.161us 1 1 100.00
sec_cm_mem_readback 1 1 100.00
sram_ctrl_readback_err 4.000s 2658.956us 1 1 100.00
sec_cm_mem_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 550.655us 1 1 100.00
sec_cm_addr_scramble 1 1 100.00
sram_ctrl_smoke 3.000s 550.655us 1 1 100.00
sec_cm_instr_bus_lc_gated 1 1 100.00
sram_ctrl_executable 24.000s 23196.186us 1 1 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 1 1 100.00
sram_ctrl_sec_cm 2.000s 1613.614us 1 1 100.00
sec_cm_key_global_esc 1 1 100.00
sram_ctrl_lc_escalation 34.000s 34351.460us 1 1 100.00
sec_cm_key_local_esc 1 1 100.00
sram_ctrl_sec_cm 2.000s 1613.614us 1 1 100.00
sec_cm_init_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1613.614us 1 1 100.00
sec_cm_scramble_key_sideload 1 1 100.00
sram_ctrl_smoke 3.000s 550.655us 1 1 100.00
sec_cm_tlul_fifo_ctr_redun 1 1 100.00
sram_ctrl_sec_cm 2.000s 1613.614us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sram_ctrl_stress_all_with_rand_reset 14.000s 939.809us 1 1 100.00

Error Messages

   Test seed line log context
UVM_ERROR (sram_ctrl_throughput_vseq.sv:66) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_ops + * + num_partial_write * * (* [*] vs * [*]) 2 test runs
sram_ctrl_max_throughput 90169400428506057689687401626278910988440215333037484885911338969756362050188 86
UVM_INFO @ 3301704499 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
sram_ctrl_throughput_w_partial_write 15346120736246428592608401385402623589355063061918156176235887965799686811602 86
UVM_INFO @ 2641899042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sram_ctrl_throughput_vseq.sv:64) [sram_ctrl_throughput_vseq] Check failed num_cycles == num_writes * * + num_reads * * - last_was_write (* [*] vs * [*]) 1 test run
sram_ctrl_throughput_w_readback 90750014150531980499110896883333631898373976920622450269358430406783269118640 86
UVM_INFO @ 2077033534 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---