Simulation Results: adc_ctrl

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 66.32 %
  • code
  • 93.63 %
  • assert
  • 92.06 %
  • func
  • 13.27 %
  • line
  • 98.03 %
  • branch
  • 96.29 %
  • cond
  • 85.81 %
  • toggle
  • 98.82 %
  • FSM
  • 89.19 %
Validation stages
V1
100.00%
V2
52.63%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 4.490s 5941.729us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 0.840s 650.802us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.950s 398.152us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 18.340s 44334.947us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.210s 1379.862us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.950s 650.749us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.950s 398.152us 1 1 100.00
adc_ctrl_csr_aliasing 1.210s 1379.862us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 0 1 0.00
adc_ctrl_filters_polled 1.040s 339.643us 0 1 0.00
filters_polled_fixed 0 1 0.00
adc_ctrl_filters_polled_fixed 0.650s 355.731us 0 1 0.00
filters_interrupt 0 1 0.00
adc_ctrl_filters_interrupt 0.730s 393.577us 0 1 0.00
filters_interrupt_fixed 0 1 0.00
adc_ctrl_filters_interrupt_fixed 0.830s 381.640us 0 1 0.00
filters_wakeup 0 1 0.00
adc_ctrl_filters_wakeup 0.890s 275.517us 0 1 0.00
filters_wakeup_fixed 0 1 0.00
adc_ctrl_filters_wakeup_fixed 0.770s 273.365us 0 1 0.00
filters_both 0 1 0.00
adc_ctrl_filters_both 1.180s 442.835us 0 1 0.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 0.910s 487.324us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 2.830s 3004.568us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 35.430s 26717.809us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 131.640s 90098.190us 1 1 100.00
stress_all 0 1 0.00
adc_ctrl_stress_all 2.460s 4913.572us 0 1 0.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.080s 390.083us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.820s 542.641us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 1.480s 640.712us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 1.480s 640.712us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.840s 650.802us 1 1 100.00
adc_ctrl_csr_rw 0.950s 398.152us 1 1 100.00
adc_ctrl_csr_aliasing 1.210s 1379.862us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.470s 4894.802us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 0.840s 650.802us 1 1 100.00
adc_ctrl_csr_rw 0.950s 398.152us 1 1 100.00
adc_ctrl_csr_aliasing 1.210s 1379.862us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.470s 4894.802us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 2.100s 3937.005us 1 1 100.00
adc_ctrl_tl_intg_err 3.070s 9239.045us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 3.070s 9239.045us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
adc_ctrl_stress_all_with_rand_reset 3.020s 1807.551us 0 1 0.00

Error Messages

   Test seed line log context
UVM_FATAL (adc_ctrl_filter_cfg.sv:57) [adc_ctrl_filter_cfg::make] Backwards min_v/max_v range of [*, *] 10 test runs
adc_ctrl_filters_polled 41918745704802249314068917801567145810376377366279734063606331129587863269777 386
UVM_INFO @ 339643169 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_polled_fixed 41794481261976692426239737842404674335947858611002486079467975589305378554585 386
UVM_INFO @ 355730624 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt 85671007319658417898844863993374717438915562140989753756373826156271271744855 386
UVM_INFO @ 393576546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_interrupt_fixed 16611499239011357964793796625430915152184950129589832664125183921266580469050 386
UVM_INFO @ 381640262 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup 4188845042218683545864568322817722838477973988134401449843367111796758734475 386
UVM_INFO @ 275517184 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_wakeup_fixed 92291094315357623307987106035734521622435045781403967522857001541068739380971 386
UVM_INFO @ 273365396 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_clock_gating 27841091069091765665170976991988205890614101022271942582419091409574659556846 386
UVM_INFO @ 487323813 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_filters_both 82982887466212111070360865928847422907675116013782281136162439981475931633459 386
UVM_INFO @ 442835427 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all_with_rand_reset 92767697221514736657423879437749659803606158312622154194743244258335221787902 405
UVM_INFO @ 1807550810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
adc_ctrl_stress_all 95310356377727583667862221945316234669384802390665233968884982539046137118634 399
UVM_INFO @ 4913571558 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---