Simulation Results: aes/unmasked

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • Total
  • 87.37 %
  • code
  • 90.17 %
  • assert
  • 97.92 %
  • func
  • 74.00 %
  • block
  • 90.23 %
  • line
  • 92.60 %
  • branch
  • 81.22 %
  • toggle
  • 97.99 %
  • FSM
  • 88.89 %
Validation stages
V1
100.00%
V2
100.00%
V2S
87.50%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
wake_up 1 1 100.00
aes_wake_up 1.000s 66.049us 1 1 100.00
smoke 1 1 100.00
aes_smoke 1.000s 96.735us 1 1 100.00
csr_hw_reset 1 1 100.00
aes_csr_hw_reset 2.000s 98.812us 1 1 100.00
csr_rw 1 1 100.00
aes_csr_rw 2.000s 77.097us 1 1 100.00
csr_bit_bash 1 1 100.00
aes_csr_bit_bash 5.000s 260.165us 1 1 100.00
csr_aliasing 1 1 100.00
aes_csr_aliasing 1.000s 651.096us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
aes_csr_mem_rw_with_rand_reset 2.000s 58.905us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
aes_csr_rw 2.000s 77.097us 1 1 100.00
aes_csr_aliasing 1.000s 651.096us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
algorithm 3 3 100.00
aes_smoke 1.000s 96.735us 1 1 100.00
aes_config_error 2.000s 71.042us 1 1 100.00
aes_stress 2.000s 168.972us 1 1 100.00
key_length 3 3 100.00
aes_smoke 1.000s 96.735us 1 1 100.00
aes_config_error 2.000s 71.042us 1 1 100.00
aes_stress 2.000s 168.972us 1 1 100.00
back2back 2 2 100.00
aes_stress 2.000s 168.972us 1 1 100.00
aes_b2b 3.000s 86.037us 1 1 100.00
backpressure 1 1 100.00
aes_stress 2.000s 168.972us 1 1 100.00
multi_message 4 4 100.00
aes_smoke 1.000s 96.735us 1 1 100.00
aes_config_error 2.000s 71.042us 1 1 100.00
aes_stress 2.000s 168.972us 1 1 100.00
aes_alert_reset 2.000s 67.603us 1 1 100.00
failure_test 3 3 100.00
aes_man_cfg_err 1.000s 119.304us 1 1 100.00
aes_config_error 2.000s 71.042us 1 1 100.00
aes_alert_reset 2.000s 67.603us 1 1 100.00
trigger_clear_test 1 1 100.00
aes_clear 2.000s 59.383us 1 1 100.00
nist_test_vectors 1 1 100.00
aes_nist_vectors 5.000s 1364.636us 1 1 100.00
reset_recovery 1 1 100.00
aes_alert_reset 2.000s 67.603us 1 1 100.00
stress 1 1 100.00
aes_stress 2.000s 168.972us 1 1 100.00
sideload 2 2 100.00
aes_stress 2.000s 168.972us 1 1 100.00
aes_sideload 2.000s 67.071us 1 1 100.00
deinitialization 1 1 100.00
aes_deinit 3.000s 65.607us 1 1 100.00
stress_all 1 1 100.00
aes_stress_all 17.000s 1071.676us 1 1 100.00
alert_test 1 1 100.00
aes_alert_test 2.000s 113.900us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
aes_tl_errors 3.000s 703.371us 1 1 100.00
tl_d_illegal_access 1 1 100.00
aes_tl_errors 3.000s 703.371us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
aes_csr_hw_reset 2.000s 98.812us 1 1 100.00
aes_csr_rw 2.000s 77.097us 1 1 100.00
aes_csr_aliasing 1.000s 651.096us 1 1 100.00
aes_same_csr_outstanding 2.000s 149.749us 1 1 100.00
tl_d_partial_access 4 4 100.00
aes_csr_hw_reset 2.000s 98.812us 1 1 100.00
aes_csr_rw 2.000s 77.097us 1 1 100.00
aes_csr_aliasing 1.000s 651.096us 1 1 100.00
aes_same_csr_outstanding 2.000s 149.749us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reseeding 0 1 0.00
aes_reseed 1.000s 34.909us 0 1 0.00
fault_inject 2 3 66.67
aes_fi 2.000s 118.400us 0 1 0.00
aes_control_fi 1.000s 95.324us 1 1 100.00
aes_cipher_fi 2.000s 53.846us 1 1 100.00
shadow_reg_update_error 1 1 100.00
aes_shadow_reg_errors 1.000s 97.950us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
aes_shadow_reg_errors 1.000s 97.950us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
aes_shadow_reg_errors 1.000s 97.950us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
aes_shadow_reg_errors 1.000s 97.950us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
aes_shadow_reg_errors_with_csr_rw 2.000s 84.109us 1 1 100.00
tl_intg_err 2 2 100.00
aes_sec_cm 2.000s 1134.628us 1 1 100.00
aes_tl_intg_err 2.000s 200.109us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
aes_tl_intg_err 2.000s 200.109us 1 1 100.00
sec_cm_lc_escalate_en_intersig_mubi 1 1 100.00
aes_alert_reset 2.000s 67.603us 1 1 100.00
sec_cm_main_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 97.950us 1 1 100.00
sec_cm_gcm_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 97.950us 1 1 100.00
sec_cm_main_config_sparse 4 4 100.00
aes_smoke 1.000s 96.735us 1 1 100.00
aes_stress 2.000s 168.972us 1 1 100.00
aes_alert_reset 2.000s 67.603us 1 1 100.00
aes_core_fi 2.000s 77.056us 1 1 100.00
sec_cm_gcm_config_sparse 3 3 100.00
aes_config_error 2.000s 71.042us 1 1 100.00
aes_stress 2.000s 168.972us 1 1 100.00
aes_core_fi 2.000s 77.056us 1 1 100.00
sec_cm_aux_config_shadow 1 1 100.00
aes_shadow_reg_errors 1.000s 97.950us 1 1 100.00
sec_cm_aux_config_regwen 2 2 100.00
aes_readability 2.000s 91.269us 1 1 100.00
aes_stress 2.000s 168.972us 1 1 100.00
sec_cm_key_sideload 2 2 100.00
aes_stress 2.000s 168.972us 1 1 100.00
aes_sideload 2.000s 67.071us 1 1 100.00
sec_cm_key_sw_unreadable 1 1 100.00
aes_readability 2.000s 91.269us 1 1 100.00
sec_cm_data_reg_sw_unreadable 1 1 100.00
aes_readability 2.000s 91.269us 1 1 100.00
sec_cm_key_sec_wipe 1 1 100.00
aes_readability 2.000s 91.269us 1 1 100.00
sec_cm_iv_config_sec_wipe 1 1 100.00
aes_readability 2.000s 91.269us 1 1 100.00
sec_cm_data_reg_sec_wipe 1 1 100.00
aes_readability 2.000s 91.269us 1 1 100.00
sec_cm_data_reg_key_sca 1 1 100.00
aes_stress 2.000s 168.972us 1 1 100.00
sec_cm_key_masking 1 1 100.00
aes_stress 2.000s 168.972us 1 1 100.00
sec_cm_main_fsm_sparse 0 1 0.00
aes_fi 2.000s 118.400us 0 1 0.00
sec_cm_main_fsm_redun 3 4 75.00
aes_fi 2.000s 118.400us 0 1 0.00
aes_control_fi 1.000s 95.324us 1 1 100.00
aes_cipher_fi 2.000s 53.846us 1 1 100.00
aes_ctr_fi 2.000s 71.957us 1 1 100.00
sec_cm_cipher_fsm_sparse 0 1 0.00
aes_fi 2.000s 118.400us 0 1 0.00
sec_cm_cipher_fsm_redun 2 3 66.67
aes_fi 2.000s 118.400us 0 1 0.00
aes_control_fi 1.000s 95.324us 1 1 100.00
aes_cipher_fi 2.000s 53.846us 1 1 100.00
sec_cm_cipher_ctr_redun 1 1 100.00
aes_cipher_fi 2.000s 53.846us 1 1 100.00
sec_cm_ctr_fsm_sparse 0 1 0.00
aes_fi 2.000s 118.400us 0 1 0.00
sec_cm_ctr_fsm_redun 2 3 66.67
aes_fi 2.000s 118.400us 0 1 0.00
aes_control_fi 1.000s 95.324us 1 1 100.00
aes_ctr_fi 2.000s 71.957us 1 1 100.00
sec_cm_ghash_fsm_sparse 0 1 0.00
aes_fi 2.000s 118.400us 0 1 0.00
sec_cm_ctrl_sparse 3 4 75.00
aes_fi 2.000s 118.400us 0 1 0.00
aes_control_fi 1.000s 95.324us 1 1 100.00
aes_cipher_fi 2.000s 53.846us 1 1 100.00
aes_ctr_fi 2.000s 71.957us 1 1 100.00
sec_cm_main_fsm_global_esc 1 1 100.00
aes_alert_reset 2.000s 67.603us 1 1 100.00
sec_cm_main_fsm_local_esc 3 4 75.00
aes_fi 2.000s 118.400us 0 1 0.00
aes_control_fi 1.000s 95.324us 1 1 100.00
aes_cipher_fi 2.000s 53.846us 1 1 100.00
aes_ctr_fi 2.000s 71.957us 1 1 100.00
sec_cm_cipher_fsm_local_esc 3 4 75.00
aes_fi 2.000s 118.400us 0 1 0.00
aes_control_fi 1.000s 95.324us 1 1 100.00
aes_cipher_fi 2.000s 53.846us 1 1 100.00
aes_ctr_fi 2.000s 71.957us 1 1 100.00
sec_cm_ctr_fsm_local_esc 2 3 66.67
aes_fi 2.000s 118.400us 0 1 0.00
aes_control_fi 1.000s 95.324us 1 1 100.00
aes_ctr_fi 2.000s 71.957us 1 1 100.00
sec_cm_ghash_fsm_local_esc 0 1 0.00
aes_fi 2.000s 118.400us 0 1 0.00
sec_cm_data_reg_local_esc 2 3 66.67
aes_fi 2.000s 118.400us 0 1 0.00
aes_control_fi 1.000s 95.324us 1 1 100.00
aes_cipher_fi 2.000s 53.846us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
aes_stress_all_with_rand_reset 2.000s 13.044us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'parent_sequence' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues 1 test run
aes_reseed 111414980674878231113387966477124026832324671131849392038785486756379430282209 5295
UVM_INFO @ 34908864 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (aes_scoreboard.sv:926) scoreboard [scoreboard] 1 test run
aes_fi 109325584774363126856961626676926419137070577389519823239252725010937365575674 5272
----| NO FAILURES BUT NUMBER OF EXPECTED MESSAGES DOES NOT MATCH ACTUAL
----| Expected: 4
----| Seen: 3
----| Expected corrupted: 0
UVM_FATAL (cip_base_vseq.sv:1220) [aes_common_vseq] Check failed (vseq_done) 1 test run
aes_stress_all_with_rand_reset 11718068610708261000416018164419040959403435548496546630499858528061735973876 135
UVM_INFO @ 13044066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---