Simulation Results: alert_handler

 
09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]
Coverage statistics
  • Total
  • 88.88 %
  • code
  • 89.96 %
  • assert
  • 98.02 %
  • func
  • 78.65 %
  • line
  • 99.65 %
  • branch
  • 98.30 %
  • cond
  • 91.00 %
  • toggle
  • 86.65 %
  • FSM
  • 74.19 %
Validation stages
V1
100.00%
V2
89.47%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
alert_handler_smoke 43.380s 5789.158us 1 1 100.00
csr_hw_reset 1 1 100.00
alert_handler_csr_hw_reset 5.900s 117.360us 1 1 100.00
csr_rw 1 1 100.00
alert_handler_csr_rw 3.400s 353.865us 1 1 100.00
csr_bit_bash 1 1 100.00
alert_handler_csr_bit_bash 129.370s 18375.699us 1 1 100.00
csr_aliasing 1 1 100.00
alert_handler_csr_aliasing 158.100s 4290.482us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
alert_handler_csr_mem_rw_with_rand_reset 3.470s 42.415us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
alert_handler_csr_rw 3.400s 353.865us 1 1 100.00
alert_handler_csr_aliasing 158.100s 4290.482us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
esc_accum 1 1 100.00
alert_handler_esc_alert_accum 85.250s 17332.607us 1 1 100.00
esc_timeout 1 1 100.00
alert_handler_esc_intr_timeout 16.390s 1350.480us 1 1 100.00
entropy 1 1 100.00
alert_handler_entropy 1621.020s 94709.874us 1 1 100.00
sig_int_fail 1 1 100.00
alert_handler_sig_int_fail 33.920s 1925.564us 1 1 100.00
clk_skew 1 1 100.00
alert_handler_smoke 43.380s 5789.158us 1 1 100.00
random_alerts 1 1 100.00
alert_handler_random_alerts 6.570s 2424.342us 1 1 100.00
random_classes 1 1 100.00
alert_handler_random_classes 24.090s 10851.051us 1 1 100.00
ping_timeout 0 1 0.00
alert_handler_ping_timeout 36.590s 5341.641us 0 1 0.00
lpg 2 2 100.00
alert_handler_lpg 2010.580s 245910.786us 1 1 100.00
alert_handler_lpg_stub_clk 596.160s 62032.168us 1 1 100.00
stress_all 1 1 100.00
alert_handler_stress_all 1839.870s 228423.031us 1 1 100.00
alert_handler_entropy_stress_test 0 1 0.00
alert_handler_entropy_stress 7.000s 259.816us 0 1 0.00
alert_handler_alert_accum_saturation 1 1 100.00
alert_handler_alert_accum_saturation 1.630s 52.567us 1 1 100.00
intr_test 1 1 100.00
alert_handler_intr_test 1.200s 8.913us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
alert_handler_tl_errors 4.200s 211.137us 1 1 100.00
tl_d_illegal_access 1 1 100.00
alert_handler_tl_errors 4.200s 211.137us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
alert_handler_csr_hw_reset 5.900s 117.360us 1 1 100.00
alert_handler_csr_rw 3.400s 353.865us 1 1 100.00
alert_handler_csr_aliasing 158.100s 4290.482us 1 1 100.00
alert_handler_same_csr_outstanding 7.220s 345.101us 1 1 100.00
tl_d_partial_access 4 4 100.00
alert_handler_csr_hw_reset 5.900s 117.360us 1 1 100.00
alert_handler_csr_rw 3.400s 353.865us 1 1 100.00
alert_handler_csr_aliasing 158.100s 4290.482us 1 1 100.00
alert_handler_same_csr_outstanding 7.220s 345.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
shadow_reg_update_error 1 1 100.00
alert_handler_shadow_reg_errors 51.700s 1683.221us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
alert_handler_shadow_reg_errors 51.700s 1683.221us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
alert_handler_shadow_reg_errors 51.700s 1683.221us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
alert_handler_shadow_reg_errors 51.700s 1683.221us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
alert_handler_shadow_reg_errors_with_csr_rw 608.630s 51748.099us 1 1 100.00
tl_intg_err 2 2 100.00
alert_handler_sec_cm 8.950s 1020.664us 1 1 100.00
alert_handler_tl_intg_err 42.570s 1210.082us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
alert_handler_tl_intg_err 42.570s 1210.082us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
alert_handler_shadow_reg_errors 51.700s 1683.221us 1 1 100.00
sec_cm_ping_timer_config_regwen 1 1 100.00
alert_handler_smoke 43.380s 5789.158us 1 1 100.00
sec_cm_alert_config_regwen 1 1 100.00
alert_handler_smoke 43.380s 5789.158us 1 1 100.00
sec_cm_alert_loc_config_regwen 1 1 100.00
alert_handler_smoke 43.380s 5789.158us 1 1 100.00
sec_cm_class_config_regwen 1 1 100.00
alert_handler_smoke 43.380s 5789.158us 1 1 100.00
sec_cm_alert_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 33.920s 1925.564us 1 1 100.00
sec_cm_lpg_intersig_mubi 1 1 100.00
alert_handler_lpg 2010.580s 245910.786us 1 1 100.00
sec_cm_esc_intersig_diff 1 1 100.00
alert_handler_sig_int_fail 33.920s 1925.564us 1 1 100.00
sec_cm_alert_rx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1621.020s 94709.874us 1 1 100.00
sec_cm_esc_tx_intersig_bkgn_chk 1 1 100.00
alert_handler_entropy 1621.020s 94709.874us 1 1 100.00
sec_cm_esc_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.950s 1020.664us 1 1 100.00
sec_cm_ping_timer_fsm_sparse 1 1 100.00
alert_handler_sec_cm 8.950s 1020.664us 1 1 100.00
sec_cm_esc_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.950s 1020.664us 1 1 100.00
sec_cm_ping_timer_fsm_local_esc 1 1 100.00
alert_handler_sec_cm 8.950s 1020.664us 1 1 100.00
sec_cm_esc_timer_fsm_global_esc 1 1 100.00
alert_handler_sec_cm 8.950s 1020.664us 1 1 100.00
sec_cm_accu_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.950s 1020.664us 1 1 100.00
sec_cm_esc_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.950s 1020.664us 1 1 100.00
sec_cm_ping_timer_ctr_redun 1 1 100.00
alert_handler_sec_cm 8.950s 1020.664us 1 1 100.00
sec_cm_ping_timer_lfsr_redun 1 1 100.00
alert_handler_sec_cm 8.950s 1020.664us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
alert_handler_stress_all_with_rand_reset 23.820s 2368.196us 0 1 0.00

Error Messages

   Test seed line log context
UVM_ERROR (alert_handler_scoreboard.sv:486) [scoreboard] Check failed intr_state_val == item.d_data (* [*] vs * [*]) reg name: intr_state 1 test run
alert_handler_ping_timeout 24850449513877423185704257658667297076267469546290341619693510157834912367377 96
UVM_INFO @ 5341640827 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR sequencer [alert_sender_ping_rsp_seq] Response queue overflow, response was dropped 1 test run
alert_handler_entropy_stress 45761044299756637347718299424037893426281328494277257969914947897658000572744 192
UVM_INFO @ 259816145 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (cip_base_vseq.sv:1286) [alert_handler_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. 1 test run
alert_handler_stress_all_with_rand_reset 52184087340276833866334884916779860232517506447786599417817318235696099193724 106
UVM_INFO @ 2368195936 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---