Simulation Results

Simulation Results: chip

09/07/2026 15:30:27 DVSim: v1.49.12 sha: 527817d json Branch: master Tool: vcs [unknown]

Coverage statistics

Total
74.38 %

code
84.00 %

assert
97.49 %

func
41.66 %

line
94.16 %

branch
92.43 %

cond
89.00 %

toggle
87.27 %

FSM
57.14 %

Validation stages

V1		94.44%
V2		75.81%
V2S		50.00%
V3		65.38%
unmapped		63.64%

17/18 passed

94.44 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_example_tests				4	4	100.00
	chip_sw_example_flash	171.430s	3210.248us	1	1	100.00
	chip_sw_example_rom	61.780s	1900.206us	1	1	100.00
	chip_sw_example_manufacturer	176.430s	3646.170us	1	1	100.00
	chip_sw_example_concurrency	178.640s	3467.078us	1	1	100.00
csr_hw_reset				1	1	100.00
	chip_csr_hw_reset	216.230s	7108.822us	1	1	100.00
csr_rw				1	1	100.00
	chip_csr_rw	202.740s	4086.419us	1	1	100.00
csr_bit_bash				1	1	100.00
	chip_csr_bit_bash	735.610s	12144.563us	1	1	100.00
csr_aliasing				1	1	100.00
	chip_csr_aliasing	3445.090s	28241.468us	1	1	100.00
csr_mem_rw_with_rand_reset				0	1	0.00
	chip_csr_mem_rw_with_rand_reset	60.740s	2139.261us	0	1	0.00
regwen_csr_and_corresponding_lockable_csr				2	2	100.00
	chip_csr_aliasing	3445.090s	28241.468us	1	1	100.00
	chip_csr_rw	202.740s	4086.419us	1	1	100.00
xbar_smoke				1	1	100.00
	xbar_smoke	6.690s	248.955us	1	1	100.00
chip_sw_gpio_out				1	1	100.00
	chip_sw_gpio	341.860s	5017.678us	1	1	100.00
chip_sw_gpio_in				1	1	100.00
	chip_sw_gpio	341.860s	5017.678us	1	1	100.00
chip_sw_gpio_irq				1	1	100.00
	chip_sw_gpio	341.860s	5017.678us	1	1	100.00
chip_sw_uart_tx_rx				1	1	100.00
	chip_sw_uart_tx_rx	327.210s	4456.797us	1	1	100.00
chip_sw_uart_rx_overflow				4	4	100.00
	chip_sw_uart_tx_rx	327.210s	4456.797us	1	1	100.00
	chip_sw_uart_tx_rx_idx1	367.680s	4560.381us	1	1	100.00
	chip_sw_uart_tx_rx_idx2	331.630s	3887.980us	1	1	100.00
	chip_sw_uart_tx_rx_idx3	309.390s	4836.084us	1	1	100.00
chip_sw_uart_baud_rate				1	1	100.00
	chip_sw_uart_rand_baudrate	1028.040s	9131.434us	1	1	100.00
chip_sw_uart_tx_rx_alt_clk_freq				2	2	100.00
	chip_sw_uart_tx_rx_alt_clk_freq	1067.910s	8777.311us	1	1	100.00
	chip_sw_uart_tx_rx_alt_clk_freq_low_speed	269.520s	4740.637us	1	1	100.00

210/277 passed

75.81 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_pin_mux				1	1	100.00
	chip_padctrl_attributes	202.610s	4471.004us	1	1	100.00
chip_padctrl_attributes				1	1	100.00
	chip_padctrl_attributes	202.610s	4471.004us	1	1	100.00
chip_sw_sleep_pin_mio_dio_val				0	1	0.00
	chip_sw_sleep_pin_mio_dio_val	209.130s	3551.898us	0	1	0.00
chip_sw_sleep_pin_wake				1	1	100.00
	chip_sw_sleep_pin_wake	163.100s	3106.646us	1	1	100.00
chip_sw_sleep_pin_retention				1	1	100.00
	chip_sw_sleep_pin_retention	142.780s	3054.038us	1	1	100.00
chip_sw_tap_strap_sampling				4	4	100.00
	chip_tap_straps_dev	174.070s	4399.843us	1	1	100.00
	chip_tap_straps_testunlock0	304.390s	5651.184us	1	1	100.00
	chip_tap_straps_rma	100.870s	3139.496us	1	1	100.00
	chip_tap_straps_prod	228.430s	4348.221us	1	1	100.00
chip_sw_data_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	410.370s	5680.247us	1	1	100.00
chip_sw_instruction_integrity				1	1	100.00
	chip_sw_data_integrity_escalation	410.370s	5680.247us	1	1	100.00
chip_sw_ast_clk_outputs				1	1	100.00
	chip_sw_ast_clk_outputs	533.490s	7225.873us	1	1	100.00
chip_sw_ast_clk_rst_inputs				0	1	0.00
	chip_sw_ast_clk_rst_inputs	750.870s	10669.943us	0	1	0.00
chip_sw_ast_sys_clk_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	395.580s	4592.061us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	522.310s	5104.689us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3925.690s	18717.123us	1	1	100.00
	chip_sw_aes_enc_jitter_en	162.400s	2833.868us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	677.510s	6712.158us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	152.670s	3063.383us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1149.170s	11595.025us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	168.120s	2626.951us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	267.060s	4223.706us	1	1	100.00
	chip_sw_clkmgr_jitter	152.350s	2704.746us	1	1	100.00
chip_sw_ast_usb_clk_calib				1	1	100.00
	chip_sw_usb_ast_clk_calib	149.890s	2505.041us	1	1	100.00
chip_sw_sensor_ctrl_ast_alerts				2	2	100.00
	chip_sw_sensor_ctrl_alert	471.420s	6781.534us	1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	280.390s	5820.709us	1	1	100.00
chip_sw_sensor_ctrl_ast_status				1	1	100.00
	chip_sw_sensor_ctrl_status	138.510s	2737.826us	1	1	100.00
chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup				1	1	100.00
	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	280.390s	5820.709us	1	1	100.00
chip_sw_smoketest				17	17	100.00
	chip_sw_flash_scrambling_smoketest	150.720s	2370.946us	1	1	100.00
	chip_sw_aes_smoketest	175.360s	2635.942us	1	1	100.00
	chip_sw_aon_timer_smoketest	185.440s	3478.525us	1	1	100.00
	chip_sw_clkmgr_smoketest	173.360s	2923.671us	1	1	100.00
	chip_sw_csrng_smoketest	134.200s	2882.267us	1	1	100.00
	chip_sw_entropy_src_smoketest	720.120s	6158.417us	1	1	100.00
	chip_sw_gpio_smoketest	148.130s	2512.868us	1	1	100.00
	chip_sw_hmac_smoketest	167.340s	3729.835us	1	1	100.00
	chip_sw_kmac_smoketest	169.480s	3585.417us	1	1	100.00
	chip_sw_otbn_smoketest	604.820s	4829.802us	1	1	100.00
	chip_sw_pwrmgr_smoketest	361.670s	7029.417us	1	1	100.00
	chip_sw_pwrmgr_usbdev_smoketest	315.760s	6744.999us	1	1	100.00
	chip_sw_rv_plic_smoketest	171.940s	3131.431us	1	1	100.00
	chip_sw_rv_timer_smoketest	154.980s	3057.767us	1	1	100.00
	chip_sw_rstmgr_smoketest	150.460s	2906.120us	1	1	100.00
	chip_sw_sram_ctrl_smoketest	127.170s	2591.168us	1	1	100.00
	chip_sw_uart_smoketest	137.180s	2691.141us	1	1	100.00
chip_sw_otp_smoketest				1	1	100.00
	chip_sw_otp_ctrl_smoketest	196.180s	3648.556us	1	1	100.00
chip_sw_rom_functests				0	1	0.00
	rom_keymgr_functest	272.260s	4847.144us	0	1	0.00
chip_sw_boot				1	1	100.00
	chip_sw_uart_tx_rx_bootstrap	7538.690s	61049.449us	1	1	100.00
chip_sw_secure_boot				1	1	100.00
	rom_e2e_smoke	3206.360s	14675.709us	1	1	100.00
chip_sw_rom_raw_unlock				0	1	0.00
	rom_raw_unlock	28.346s	0.000us	0	1	0.00
chip_sw_power_idle_load				0	1	0.00
	chip_sw_power_idle_load	1109.210s	15354.059us	0	1	0.00
chip_sw_power_sleep_load				0	1	0.00
	chip_sw_power_sleep_load	634.900s	15060.572us	0	1	0.00
chip_sw_exit_test_unlocked_bootstrap				1	1	100.00
	chip_sw_exit_test_unlocked_bootstrap	7019.010s	52021.037us	1	1	100.00
chip_sw_inject_scramble_seed				1	1	100.00
	chip_sw_inject_scramble_seed	7313.630s	55763.026us	1	1	100.00
tl_d_oob_addr_access				1	1	100.00
	chip_tl_errors	147.410s	3667.251us	1	1	100.00
tl_d_illegal_access				1	1	100.00
	chip_tl_errors	147.410s	3667.251us	1	1	100.00
tl_d_outstanding_access				4	4	100.00
	chip_csr_aliasing	3445.090s	28241.468us	1	1	100.00
	chip_same_csr_outstanding	2325.160s	26432.000us	1	1	100.00
	chip_csr_hw_reset	216.230s	7108.822us	1	1	100.00
	chip_csr_rw	202.740s	4086.419us	1	1	100.00
tl_d_partial_access				4	4	100.00
	chip_csr_aliasing	3445.090s	28241.468us	1	1	100.00
	chip_same_csr_outstanding	2325.160s	26432.000us	1	1	100.00
	chip_csr_hw_reset	216.230s	7108.822us	1	1	100.00
	chip_csr_rw	202.740s	4086.419us	1	1	100.00
xbar_base_random_sequence				1	1	100.00
	xbar_random	14.970s	232.909us	1	1	100.00
xbar_random_delay				6	6	100.00
	xbar_smoke_zero_delays	4.690s	52.887us	1	1	100.00
	xbar_smoke_large_delays	40.720s	7539.292us	1	1	100.00
	xbar_smoke_slow_rsp	46.560s	5831.280us	1	1	100.00
	xbar_random_zero_delays	5.940s	66.946us	1	1	100.00
	xbar_random_large_delays	291.680s	55663.301us	1	1	100.00
	xbar_random_slow_rsp	29.270s	3616.342us	1	1	100.00
xbar_unmapped_address				2	2	100.00
	xbar_unmapped_addr	4.660s	85.175us	1	1	100.00
	xbar_error_and_unmapped_addr	8.350s	110.766us	1	1	100.00
xbar_error_cases				2	2	100.00
	xbar_error_random	21.540s	1065.343us	1	1	100.00
	xbar_error_and_unmapped_addr	8.350s	110.766us	1	1	100.00
xbar_all_access_same_device				2	2	100.00
	xbar_access_same_device	37.880s	1141.108us	1	1	100.00
	xbar_access_same_device_slow_rsp	308.970s	39417.982us	1	1	100.00
xbar_all_hosts_use_same_source_id				1	1	100.00
	xbar_same_source	6.020s	71.221us	1	1	100.00
xbar_stress_all				2	2	100.00
	xbar_stress_all	256.850s	10542.581us	1	1	100.00
	xbar_stress_all_with_error	251.850s	6138.482us	1	1	100.00
xbar_stress_with_reset				2	2	100.00
	xbar_stress_all_with_rand_reset	129.850s	515.217us	1	1	100.00
	xbar_stress_all_with_reset_error	293.130s	4298.628us	1	1	100.00
rom_e2e_smoke				1	1	100.00
	rom_e2e_smoke	3206.360s	14675.709us	1	1	100.00
rom_e2e_shutdown_output				0	1	0.00
	rom_e2e_shutdown_output	483.470s	8240.378us	0	1	0.00
rom_e2e_shutdown_exception_c				0	1	0.00
	rom_e2e_shutdown_exception_c	418.750s	4954.602us	0	1	0.00
rom_e2e_boot_policy_valid				0	15	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	117.024s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_dev	18.605s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod	28.542s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	9.478s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_good_rma	10.337s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	143.605s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	7.264s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	67.571s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	28.251s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	8.047s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	126.733s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	82.022s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	62.532s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	50.598s	0.000us	0	1	0.00
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	18.484s	0.000us	0	1	0.00
rom_e2e_sigverify_always				0	15	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	17.540s	10.220us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_dev	18.340s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod	19.610s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	20.130s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_bad_rma	19.160s	10.320us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	17.620s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	19.080s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.740s	10.300us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	19.180s	10.400us	0	1	0.00
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	18.680s	10.100us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	17.150s	10.280us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	18.280s	10.260us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.920s	10.180us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	18.510s	10.120us	0	1	0.00
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	18.730s	10.120us	0	1	0.00
rom_e2e_asm_init				0	5	0.00
	rom_e2e_asm_init_test_unlocked0	66.978s	0.000us	0	1	0.00
	rom_e2e_asm_init_dev	13.438s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod	82.484s	0.000us	0	1	0.00
	rom_e2e_asm_init_prod_end	68.626s	0.000us	0	1	0.00
	rom_e2e_asm_init_rma	90.791s	0.000us	0	1	0.00
rom_e2e_keymgr_init				2	3	66.67
	rom_e2e_keymgr_init_rom_ext_meas	5762.920s	29216.889us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_no_meas	5941.470s	29244.648us	1	1	100.00
	rom_e2e_keymgr_init_rom_ext_invalid_meas	3134.300s	15769.486us	0	1	0.00
rom_e2e_static_critical				1	1	100.00
	rom_e2e_static_critical	3218.540s	18195.660us	1	1	100.00
chip_sw_adc_ctrl_debug_cable_irq				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3236.010s	34555.619us	0	1	0.00
chip_sw_adc_ctrl_sleep_debug_cable_wakeup				0	1	0.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3236.010s	34555.619us	0	1	0.00
chip_sw_aes_enc				2	2	100.00
	chip_sw_aes_enc	189.050s	2548.221us	1	1	100.00
	chip_sw_aes_enc_jitter_en	162.400s	2833.868us	1	1	100.00
chip_sw_aes_entropy				1	1	100.00
	chip_sw_aes_entropy	164.670s	3065.063us	1	1	100.00
chip_sw_aes_idle				1	1	100.00
	chip_sw_aes_idle	211.140s	3411.587us	1	1	100.00
chip_sw_aes_sideload				1	1	100.00
	chip_sw_keymgr_sideload_aes	1384.910s	10589.756us	1	1	100.00
chip_sw_alert_handler_alerts				0	1	0.00
	chip_sw_alert_test	216.150s	2826.138us	0	1	0.00
chip_sw_alert_handler_escalations				1	1	100.00
	chip_sw_alert_handler_escalation	336.610s	5875.253us	1	1	100.00
chip_sw_all_escalation_resets				1	1	100.00
	chip_sw_all_escalation_resets	440.410s	5213.904us	1	1	100.00
chip_sw_alert_handler_irqs				3	3	100.00
	chip_plic_all_irqs_0	491.470s	5070.673us	1	1	100.00
	chip_plic_all_irqs_10	257.190s	3322.524us	1	1	100.00
	chip_plic_all_irqs_20	319.660s	4321.385us	1	1	100.00
chip_sw_alert_handler_entropy				1	1	100.00
	chip_sw_alert_handler_entropy	162.470s	3574.751us	1	1	100.00
chip_sw_alert_handler_crashdump				1	1	100.00
	chip_sw_rstmgr_alert_info	958.580s	14435.321us	1	1	100.00
chip_sw_alert_handler_ping_timeout				1	1	100.00
	chip_sw_alert_handler_ping_timeout	315.920s	5269.578us	1	1	100.00
chip_sw_alert_handler_lpg_sleep_mode_alerts				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_alerts	101.970s	2991.940us	0	1	0.00
chip_sw_alert_handler_lpg_sleep_mode_pings				0	1	0.00
	chip_sw_alert_handler_lpg_sleep_mode_pings	14400.140s	0.000us	0	1	0.00
chip_sw_alert_handler_lpg_clock_off				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	745.950s	7057.548us	1	1	100.00
chip_sw_alert_handler_lpg_reset_toggle				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1050.700s	8343.161us	1	1	100.00
chip_sw_alert_handler_ping_ok				1	1	100.00
	chip_sw_alert_handler_ping_ok	737.480s	8025.677us	1	1	100.00
chip_sw_alert_handler_reverse_ping_in_deep_sleep				1	1	100.00
	chip_sw_alert_handler_reverse_ping_in_deep_sleep	9383.540s	255370.800us	1	1	100.00
chip_sw_aon_timer_wakeup_irq				1	1	100.00
	chip_sw_aon_timer_irq	260.630s	4436.374us	1	1	100.00
chip_sw_aon_timer_sleep_wakeup				1	1	100.00
	chip_sw_pwrmgr_smoketest	361.670s	7029.417us	1	1	100.00
chip_sw_aon_timer_wdog_bark_irq				1	1	100.00
	chip_sw_aon_timer_irq	260.630s	4436.374us	1	1	100.00
chip_sw_aon_timer_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	449.860s	7789.624us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_bite_reset				1	1	100.00
	chip_sw_aon_timer_wdog_bite_reset	449.860s	7789.624us	1	1	100.00
chip_sw_aon_timer_sleep_wdog_sleep_pause				1	1	100.00
	chip_sw_aon_timer_sleep_wdog_sleep_pause	271.000s	7428.753us	1	1	100.00
chip_sw_aon_timer_wdog_lc_escalate				1	1	100.00
	chip_sw_aon_timer_wdog_lc_escalate	337.400s	4522.300us	1	1	100.00
chip_sw_clkmgr_idle_trans				4	4	100.00
	chip_sw_otbn_randomness	631.110s	6345.204us	1	1	100.00
	chip_sw_aes_idle	211.140s	3411.587us	1	1	100.00
	chip_sw_hmac_enc_idle	193.110s	3522.225us	1	1	100.00
	chip_sw_kmac_idle	131.960s	2875.334us	1	1	100.00
chip_sw_clkmgr_off_trans				4	4	100.00
	chip_sw_clkmgr_off_aes_trans	260.140s	4204.656us	1	1	100.00
	chip_sw_clkmgr_off_hmac_trans	266.380s	3916.992us	1	1	100.00
	chip_sw_clkmgr_off_kmac_trans	273.050s	4902.293us	1	1	100.00
	chip_sw_clkmgr_off_otbn_trans	353.910s	5212.072us	1	1	100.00
chip_sw_clkmgr_off_peri				1	1	100.00
	chip_sw_clkmgr_off_peri	707.460s	10808.047us	1	1	100.00
chip_sw_clkmgr_div				7	7	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	427.080s	4279.639us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	376.810s	4753.233us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	363.340s	4083.423us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	386.380s	5220.652us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	423.040s	4105.157us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	414.030s	4660.876us	1	1	100.00
	chip_sw_ast_clk_outputs	533.490s	7225.873us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_lc				1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	699.220s	11830.508us	1	1	100.00
chip_sw_clkmgr_external_clk_src_for_sw				2	2	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	363.340s	4083.423us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	386.380s	5220.652us	1	1	100.00
chip_sw_clkmgr_jitter				10	10	100.00
	chip_sw_flash_ctrl_ops_jitter_en	395.580s	4592.061us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	522.310s	5104.689us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3925.690s	18717.123us	1	1	100.00
	chip_sw_aes_enc_jitter_en	162.400s	2833.868us	1	1	100.00
	chip_sw_edn_entropy_reqs_jitter	677.510s	6712.158us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	152.670s	3063.383us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1149.170s	11595.025us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	168.120s	2626.951us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	267.060s	4223.706us	1	1	100.00
	chip_sw_clkmgr_jitter	152.350s	2704.746us	1	1	100.00
chip_sw_clkmgr_extended_range				11	11	100.00
	chip_sw_clkmgr_jitter_reduced_freq	154.510s	3192.360us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	358.470s	4756.300us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en_reduced_freq	546.450s	6865.497us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	4320.440s	25011.396us	1	1	100.00
	chip_sw_aes_enc_jitter_en_reduced_freq	154.940s	3228.331us	1	1	100.00
	chip_sw_hmac_enc_jitter_en_reduced_freq	176.060s	2880.717us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	495.400s	6942.460us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	160.630s	3050.614us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	294.620s	5912.877us	1	1	100.00
	chip_sw_flash_init_reduced_freq	1102.600s	23568.693us	1	1	100.00
	chip_sw_csrng_edn_concurrency_reduced_freq	1809.120s	15673.037us	1	1	100.00
chip_sw_clkmgr_deep_sleep_frequency				1	1	100.00
	chip_sw_ast_clk_outputs	533.490s	7225.873us	1	1	100.00
chip_sw_clkmgr_sleep_frequency				1	1	100.00
	chip_sw_clkmgr_sleep_frequency	324.740s	4928.910us	1	1	100.00
chip_sw_clkmgr_reset_frequency				1	1	100.00
	chip_sw_clkmgr_reset_frequency	289.020s	3801.123us	1	1	100.00
chip_sw_clkmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	440.410s	5213.904us	1	1	100.00
chip_sw_clkmgr_alert_handler_clock_enables				1	1	100.00
	chip_sw_alert_handler_lpg_clkoff	745.950s	7057.548us	1	1	100.00
chip_sw_csrng_edn_cmd				1	1	100.00
	chip_sw_entropy_src_csrng	2283.820s	24467.924us	1	1	100.00
chip_sw_csrng_fuse_en_sw_app_read				1	1	100.00
	chip_sw_csrng_fuse_en_sw_app_read_test	309.660s	5775.016us	1	1	100.00
chip_sw_csrng_lc_hw_debug_en				1	1	100.00
	chip_sw_csrng_lc_hw_debug_en_test	514.110s	7146.309us	1	1	100.00
chip_sw_csrng_known_answer_tests				1	1	100.00
	chip_sw_csrng_kat_test	165.690s	2849.378us	1	1	100.00
chip_sw_edn_entropy_reqs				3	3	100.00
	chip_sw_csrng_edn_concurrency	4298.540s	23051.213us	1	1	100.00
	chip_sw_entropy_src_ast_rng_req	162.220s	2499.189us	1	1	100.00
	chip_sw_edn_entropy_reqs	722.260s	6657.771us	1	1	100.00
chip_sw_entropy_src_ast_rng_req				1	1	100.00
	chip_sw_entropy_src_ast_rng_req	162.220s	2499.189us	1	1	100.00
chip_sw_entropy_src_csrng				1	1	100.00
	chip_sw_entropy_src_csrng	2283.820s	24467.924us	1	1	100.00
chip_sw_entropy_src_known_answer_tests				1	1	100.00
	chip_sw_entropy_src_kat_test	147.040s	2747.367us	1	1	100.00
chip_sw_flash_init				1	1	100.00
	chip_sw_flash_init	1132.350s	23053.062us	1	1	100.00
chip_sw_flash_host_access				2	2	100.00
	chip_sw_flash_ctrl_access	523.710s	5577.726us	1	1	100.00
	chip_sw_flash_ctrl_access_jitter_en	522.310s	5104.689us	1	1	100.00
chip_sw_flash_ctrl_ops				2	2	100.00
	chip_sw_flash_ctrl_ops	339.020s	3858.601us	1	1	100.00
	chip_sw_flash_ctrl_ops_jitter_en	395.580s	4592.061us	1	1	100.00
chip_sw_flash_rma_unlocked				1	1	100.00
	chip_sw_flash_rma_unlocked	3509.210s	42878.159us	1	1	100.00
chip_sw_flash_scramble				1	1	100.00
	chip_sw_flash_init	1132.350s	23053.062us	1	1	100.00
chip_sw_flash_idle_low_power				1	1	100.00
	chip_sw_flash_ctrl_idle_low_power	260.990s	3999.308us	1	1	100.00
chip_sw_flash_keymgr_seeds				1	1	100.00
	chip_sw_keymgr_key_derivation	1512.880s	12216.231us	1	1	100.00
chip_sw_flash_lc_creator_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	135.640s	3433.309us	0	1	0.00
chip_sw_flash_creator_seed_wipe_on_rma				1	1	100.00
	chip_sw_flash_rma_unlocked	3509.210s	42878.159us	1	1	100.00
chip_sw_flash_lc_owner_seed_sw_rw_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	135.640s	3433.309us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	135.640s	3433.309us	0	1	0.00
chip_sw_flash_lc_iso_part_sw_wr_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	135.640s	3433.309us	0	1	0.00
chip_sw_flash_lc_seed_hw_rd_en				0	1	0.00
	chip_sw_flash_ctrl_lc_rw_en	135.640s	3433.309us	0	1	0.00
chip_sw_flash_lc_escalate_en				1	1	100.00
	chip_sw_all_escalation_resets	440.410s	5213.904us	1	1	100.00
chip_sw_flash_prim_tl_access				1	1	100.00
	chip_prim_tl_access	105.320s	3507.942us	1	1	100.00
chip_sw_flash_ctrl_clock_freqs				1	1	100.00
	chip_sw_flash_ctrl_clock_freqs	532.660s	5245.903us	1	1	100.00
chip_sw_flash_ctrl_escalation_reset				1	1	100.00
	chip_sw_flash_crash_alert	353.220s	5545.068us	1	1	100.00
chip_sw_flash_ctrl_write_clear				1	1	100.00
	chip_sw_flash_crash_alert	353.220s	5545.068us	1	1	100.00
chip_sw_hmac_enc				2	2	100.00
	chip_sw_hmac_enc	131.050s	3123.651us	1	1	100.00
	chip_sw_hmac_enc_jitter_en	152.670s	3063.383us	1	1	100.00
chip_sw_hmac_idle				1	1	100.00
	chip_sw_hmac_enc_idle	193.110s	3522.225us	1	1	100.00
chip_sw_hmac_all_configurations				1	1	100.00
	chip_sw_hmac_oneshot	683.660s	5973.433us	1	1	100.00
chip_sw_hmac_multistream_mode				0	1	0.00
	chip_sw_hmac_multistream	1656.510s	12026.861us	0	1	0.00
chip_sw_i2c_host_tx_rx				3	3	100.00
	chip_sw_i2c_host_tx_rx	455.450s	5899.423us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx1	348.000s	5220.162us	1	1	100.00
	chip_sw_i2c_host_tx_rx_idx2	379.460s	4878.922us	1	1	100.00
chip_sw_i2c_device_tx_rx				1	1	100.00
	chip_sw_i2c_device_tx_rx	256.220s	3870.113us	1	1	100.00
chip_sw_keymgr_key_derivation				2	2	100.00
	chip_sw_keymgr_key_derivation	1512.880s	12216.231us	1	1	100.00
	chip_sw_keymgr_key_derivation_jitter_en	1149.170s	11595.025us	1	1	100.00
chip_sw_keymgr_sideload_kmac				1	1	100.00
	chip_sw_keymgr_sideload_kmac	1571.500s	12528.889us	1	1	100.00
chip_sw_keymgr_sideload_aes				1	1	100.00
	chip_sw_keymgr_sideload_aes	1384.910s	10589.756us	1	1	100.00
chip_sw_keymgr_sideload_otbn				0	1	0.00
	chip_sw_keymgr_sideload_otbn	4528.680s	20026.630us	0	1	0.00
chip_sw_kmac_enc				3	3	100.00
	chip_sw_kmac_mode_cshake	161.410s	3267.664us	1	1	100.00
	chip_sw_kmac_mode_kmac	204.190s	3265.935us	1	1	100.00
	chip_sw_kmac_mode_kmac_jitter_en	168.120s	2626.951us	1	1	100.00
chip_sw_kmac_app_keymgr				1	1	100.00
	chip_sw_keymgr_key_derivation	1512.880s	12216.231us	1	1	100.00
chip_sw_kmac_app_lc				1	1	100.00
	chip_sw_lc_ctrl_transition	319.800s	6812.290us	1	1	100.00
chip_sw_kmac_app_rom				1	1	100.00
	chip_sw_kmac_app_rom	174.860s	3143.862us	1	1	100.00
chip_sw_kmac_entropy				0	1	0.00
	chip_sw_kmac_entropy	1501.200s	12018.564us	0	1	0.00
chip_sw_kmac_idle				1	1	100.00
	chip_sw_kmac_idle	131.960s	2875.334us	1	1	100.00
chip_sw_lc_ctrl_alert_handler_escalation				1	1	100.00
	chip_sw_alert_handler_escalation	336.610s	5875.253us	1	1	100.00
chip_sw_lc_ctrl_jtag_access				3	3	100.00
	chip_tap_straps_dev	174.070s	4399.843us	1	1	100.00
	chip_tap_straps_rma	100.870s	3139.496us	1	1	100.00
	chip_tap_straps_prod	228.430s	4348.221us	1	1	100.00
chip_sw_lc_ctrl_otp_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	202.320s	3033.637us	1	1	100.00
chip_sw_lc_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	319.800s	6812.290us	1	1	100.00
chip_sw_lc_ctrl_transitions				1	1	100.00
	chip_sw_lc_ctrl_transition	319.800s	6812.290us	1	1	100.00
chip_sw_lc_ctrl_kmac_req				1	1	100.00
	chip_sw_lc_ctrl_transition	319.800s	6812.290us	1	1	100.00
chip_sw_lc_ctrl_key_div				1	1	100.00
	chip_sw_keymgr_key_derivation_prod	1736.750s	12717.975us	1	1	100.00
chip_sw_lc_ctrl_broadcast				20	22	90.91
	chip_sw_flash_ctrl_lc_rw_en	135.640s	3433.309us	0	1	0.00
	chip_sw_flash_rma_unlocked	3509.210s	42878.159us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	237.590s	3702.820us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	442.790s	7544.818us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	467.560s	7305.282us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	485.450s	7515.217us	0	1	0.00
	chip_sw_lc_ctrl_transition	319.800s	6812.290us	1	1	100.00
	chip_sw_keymgr_key_derivation	1512.880s	12216.231us	1	1	100.00
	chip_sw_rom_ctrl_integrity_check	357.330s	9902.140us	1	1	100.00
	chip_sw_sram_ctrl_execution_main	639.820s	10427.163us	1	1	100.00
	chip_prim_tl_access	105.320s	3507.942us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_lc	699.220s	11830.508us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	427.080s	4279.639us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	376.810s	4753.233us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	363.340s	4083.423us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	386.380s	5220.652us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	423.040s	4105.157us	1	1	100.00
	chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	414.030s	4660.876us	1	1	100.00
	chip_tap_straps_dev	174.070s	4399.843us	1	1	100.00
	chip_tap_straps_rma	100.870s	3139.496us	1	1	100.00
	chip_tap_straps_prod	228.430s	4348.221us	1	1	100.00
	chip_rv_dm_lc_disabled	193.370s	8996.919us	1	1	100.00
chip_lc_scrap				4	4	100.00
	chip_sw_lc_ctrl_rma_to_scrap	136.230s	3190.929us	1	1	100.00
	chip_sw_lc_ctrl_raw_to_scrap	88.040s	2889.376us	1	1	100.00
	chip_sw_lc_ctrl_test_locked0_to_scrap	85.850s	2794.490us	1	1	100.00
	chip_sw_lc_ctrl_rand_to_scrap	150.220s	3280.432us	1	1	100.00
chip_lc_test_locked				2	2	100.00
	chip_sw_lc_walkthrough_testunlocks	1441.730s	25375.779us	1	1	100.00
	chip_rv_dm_lc_disabled	193.370s	8996.919us	1	1	100.00
chip_sw_lc_walkthrough				1	5	20.00
	chip_sw_lc_walkthrough_dev	581.500s	11147.379us	0	1	0.00
	chip_sw_lc_walkthrough_prod	762.190s	10112.629us	0	1	0.00
	chip_sw_lc_walkthrough_prodend	823.900s	26565.030us	0	1	0.00
	chip_sw_lc_walkthrough_rma	396.450s	5996.597us	0	1	0.00
	chip_sw_lc_walkthrough_testunlocks	1441.730s	25375.779us	1	1	100.00
chip_sw_lc_ctrl_volatile_raw_unlock				2	3	66.67
	chip_sw_lc_ctrl_volatile_raw_unlock	84.760s	2550.453us	1	1	100.00
	chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	69.000s	2450.691us	1	1	100.00
	rom_volatile_raw_unlock	90.993s	0.000us	0	1	0.00
chip_sw_otbn_op				2	2	100.00
	chip_sw_otbn_ecdsa_op_irq	3840.310s	17464.119us	1	1	100.00
	chip_sw_otbn_ecdsa_op_irq_jitter_en	3925.690s	18717.123us	1	1	100.00
chip_sw_otbn_rnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	631.110s	6345.204us	1	1	100.00
chip_sw_otbn_urnd_entropy				1	1	100.00
	chip_sw_otbn_randomness	631.110s	6345.204us	1	1	100.00
chip_sw_otbn_idle				1	1	100.00
	chip_sw_otbn_randomness	631.110s	6345.204us	1	1	100.00
chip_sw_otbn_mem_scramble				1	1	100.00
	chip_sw_otbn_mem_scramble	282.540s	4030.983us	1	1	100.00
chip_otp_ctrl_init				1	1	100.00
	chip_sw_lc_ctrl_transition	319.800s	6812.290us	1	1	100.00
chip_sw_otp_ctrl_keys				5	5	100.00
	chip_sw_flash_init	1132.350s	23053.062us	1	1	100.00
	chip_sw_otbn_mem_scramble	282.540s	4030.983us	1	1	100.00
	chip_sw_keymgr_key_derivation	1512.880s	12216.231us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	398.910s	5872.812us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	125.170s	2753.923us	1	1	100.00
chip_sw_otp_ctrl_entropy				5	5	100.00
	chip_sw_flash_init	1132.350s	23053.062us	1	1	100.00
	chip_sw_otbn_mem_scramble	282.540s	4030.983us	1	1	100.00
	chip_sw_keymgr_key_derivation	1512.880s	12216.231us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access	398.910s	5872.812us	1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	125.170s	2753.923us	1	1	100.00
chip_sw_otp_ctrl_program				1	1	100.00
	chip_sw_lc_ctrl_transition	319.800s	6812.290us	1	1	100.00
chip_sw_otp_ctrl_program_error				1	1	100.00
	chip_sw_lc_ctrl_program_error	360.180s	5155.032us	1	1	100.00
chip_sw_otp_ctrl_hw_cfg0				1	1	100.00
	chip_sw_lc_ctrl_otp_hw_cfg0	202.320s	3033.637us	1	1	100.00
chip_sw_otp_ctrl_lc_signals				5	6	83.33
	chip_sw_otp_ctrl_lc_signals_test_unlocked0	237.590s	3702.820us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_dev	442.790s	7544.818us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_prod	467.560s	7305.282us	1	1	100.00
	chip_sw_otp_ctrl_lc_signals_rma	485.450s	7515.217us	0	1	0.00
	chip_sw_lc_ctrl_transition	319.800s	6812.290us	1	1	100.00
	chip_prim_tl_access	105.320s	3507.942us	1	1	100.00
chip_sw_otp_prim_tl_access				1	1	100.00
	chip_prim_tl_access	105.320s	3507.942us	1	1	100.00
chip_sw_otp_ctrl_dai_lock				1	1	100.00
	chip_sw_otp_ctrl_dai_lock	848.330s	7687.125us	1	1	100.00
chip_sw_pwrmgr_external_full_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	56.830s	2547.405us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_wake_ups	1019.810s	28063.753us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_wake_ups	259.010s	7590.588us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_por_reset				0	1	0.00
	chip_sw_pwrmgr_deep_sleep_por_reset	327.070s	7948.047us	0	1	0.00
chip_sw_pwrmgr_normal_sleep_por_reset				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_por_reset	427.200s	6954.361us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_wake_ups				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_all_wake_ups	771.320s	21893.472us	1	1	100.00
chip_sw_pwrmgr_deep_sleep_all_reset_reqs				1	2	50.00
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	208.690s	5983.416us	0	1	0.00
	chip_sw_aon_timer_wdog_bite_reset	449.860s	7789.624us	1	1	100.00
chip_sw_pwrmgr_normal_sleep_all_reset_reqs				1	1	100.00
	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	605.580s	9904.504us	1	1	100.00
chip_sw_pwrmgr_wdog_reset				1	1	100.00
	chip_sw_pwrmgr_wdog_reset	309.450s	4166.609us	1	1	100.00
chip_sw_pwrmgr_aon_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_full_aon_reset	56.830s	2547.405us	0	1	0.00
chip_sw_pwrmgr_main_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_main_power_glitch_reset	299.620s	4708.248us	1	1	100.00
chip_sw_pwrmgr_random_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	952.790s	15643.697us	0	1	0.00
chip_sw_pwrmgr_deep_sleep_power_glitch_reset				1	1	100.00
	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	330.970s	8607.082us	1	1	100.00
chip_sw_pwrmgr_sleep_power_glitch_reset				0	1	0.00
	chip_sw_pwrmgr_sleep_power_glitch_reset	133.760s	2530.756us	0	1	0.00
chip_sw_pwrmgr_random_sleep_all_reset_reqs				0	1	0.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	721.540s	13343.581us	0	1	0.00
chip_sw_pwrmgr_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	696.990s	8087.401us	1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	815.630s	9445.377us	1	1	100.00
chip_sw_pwrmgr_b2b_sleep_reset_req				1	1	100.00
	chip_sw_pwrmgr_b2b_sleep_reset_req	1823.800s	26726.333us	1	1	100.00
chip_sw_pwrmgr_sleep_disabled				1	1	100.00
	chip_sw_pwrmgr_sleep_disabled	184.760s	3644.856us	1	1	100.00
chip_sw_pwrmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	440.410s	5213.904us	1	1	100.00
chip_sw_rom_access				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	357.330s	9902.140us	1	1	100.00
chip_sw_rom_ctrl_integrity_check				1	1	100.00
	chip_sw_rom_ctrl_integrity_check	357.330s	9902.140us	1	1	100.00
chip_sw_rstmgr_non_sys_reset_info				3	4	75.00
	chip_sw_pwrmgr_all_reset_reqs	815.630s	9445.377us	1	1	100.00
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	721.540s	13343.581us	0	1	0.00
	chip_sw_pwrmgr_wdog_reset	309.450s	4166.609us	1	1	100.00
	chip_sw_pwrmgr_smoketest	361.670s	7029.417us	1	1	100.00
chip_sw_rstmgr_sys_reset_info				1	1	100.00
	chip_rv_dm_ndm_reset_req	337.260s	4585.507us	1	1	100.00
chip_sw_rstmgr_cpu_info				1	1	100.00
	chip_sw_rstmgr_cpu_info	411.100s	7552.214us	1	1	100.00
chip_sw_rstmgr_sw_req_reset				1	1	100.00
	chip_sw_rstmgr_sw_req	272.460s	4027.335us	1	1	100.00
chip_sw_rstmgr_alert_info				1	1	100.00
	chip_sw_rstmgr_alert_info	958.580s	14435.321us	1	1	100.00
chip_sw_rstmgr_sw_rst				1	1	100.00
	chip_sw_rstmgr_sw_rst	125.180s	2455.533us	1	1	100.00
chip_sw_rstmgr_escalation_reset				1	1	100.00
	chip_sw_all_escalation_resets	440.410s	5213.904us	1	1	100.00
chip_sw_rstmgr_alert_handler_reset_enables				1	1	100.00
	chip_sw_alert_handler_lpg_reset_toggle	1050.700s	8343.161us	1	1	100.00
chip_sw_nmi_irq				1	1	100.00
	chip_sw_rv_core_ibex_nmi_irq	429.970s	4787.938us	1	1	100.00
chip_sw_rv_core_ibex_rnd				1	1	100.00
	chip_sw_rv_core_ibex_rnd	440.540s	5045.635us	1	1	100.00
chip_sw_rv_core_ibex_address_translation				1	1	100.00
	chip_sw_rv_core_ibex_address_translation	158.380s	3020.055us	1	1	100.00
chip_sw_rv_core_ibex_icache_scrambled_access				1	1	100.00
	chip_sw_rv_core_ibex_icache_invalidate	125.170s	2753.923us	1	1	100.00
chip_sw_rv_core_ibex_fault_dump				1	1	100.00
	chip_sw_rstmgr_cpu_info	411.100s	7552.214us	1	1	100.00
chip_sw_rv_core_ibex_double_fault				1	1	100.00
	chip_sw_rstmgr_cpu_info	411.100s	7552.214us	1	1	100.00
chip_sw_rv_core_ibex_mcounteren_writable				1	1	100.00
	chip_sw_rv_core_ibex_mcounteren_writable	112.720s	3490.853us	1	1	100.00
chip_jtag_csr_rw				1	1	100.00
	chip_jtag_csr_rw	1137.990s	17699.307us	1	1	100.00
chip_jtag_mem_access				1	1	100.00
	chip_jtag_mem_access	978.250s	13616.201us	1	1	100.00
chip_rv_dm_ndm_reset_req				1	1	100.00
	chip_rv_dm_ndm_reset_req	337.260s	4585.507us	1	1	100.00
chip_sw_rv_dm_ndm_reset_req_when_cpu_halted				0	1	0.00
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	219.820s	3327.793us	0	1	0.00
chip_rv_dm_access_after_wakeup				0	1	0.00
	chip_sw_rv_dm_access_after_wakeup	1417.180s	12876.391us	0	1	0.00
chip_sw_rv_dm_jtag_tap_sel				1	1	100.00
	chip_tap_straps_rma	100.870s	3139.496us	1	1	100.00
chip_rv_dm_lc_disabled				1	1	100.00
	chip_rv_dm_lc_disabled	193.370s	8996.919us	1	1	100.00
chip_sw_plic_all_irqs				3	3	100.00
	chip_plic_all_irqs_0	491.470s	5070.673us	1	1	100.00
	chip_plic_all_irqs_10	257.190s	3322.524us	1	1	100.00
	chip_plic_all_irqs_20	319.660s	4321.385us	1	1	100.00
chip_sw_plic_sw_irq				1	1	100.00
	chip_sw_plic_sw_irq	162.190s	2768.041us	1	1	100.00
chip_sw_timer				1	1	100.00
	chip_sw_rv_timer_irq	160.860s	3142.500us	1	1	100.00
chip_sw_spi_device_flash_mode				1	1	100.00
	rom_e2e_smoke	3206.360s	14675.709us	1	1	100.00
chip_sw_spi_device_pass_through				1	1	100.00
	chip_sw_spi_device_pass_through	226.910s	3748.386us	1	1	100.00
chip_sw_spi_device_pass_through_collision				0	1	0.00
	chip_sw_spi_device_pass_through_collision	174.250s	3319.154us	0	1	0.00
chip_sw_spi_device_tpm				1	1	100.00
	chip_sw_spi_device_tpm	169.270s	3177.271us	1	1	100.00
chip_sw_spi_host_tx_rx				1	1	100.00
	chip_sw_spi_host_tx_rx	148.200s	3128.815us	1	1	100.00
chip_sw_sram_scrambled_access				2	2	100.00
	chip_sw_sram_ctrl_scrambled_access	398.910s	5872.812us	1	1	100.00
	chip_sw_sram_ctrl_scrambled_access_jitter_en	267.060s	4223.706us	1	1	100.00
chip_sw_sleep_sram_ret_contents				2	2	100.00
	chip_sw_sleep_sram_ret_contents_no_scramble	519.200s	8186.525us	1	1	100.00
	chip_sw_sleep_sram_ret_contents_scramble	481.380s	9048.590us	1	1	100.00
chip_sw_sram_execution				1	1	100.00
	chip_sw_sram_ctrl_execution_main	639.820s	10427.163us	1	1	100.00
chip_sw_sram_lc_escalation				2	2	100.00
	chip_sw_all_escalation_resets	440.410s	5213.904us	1	1	100.00
	chip_sw_data_integrity_escalation	410.370s	5680.247us	1	1	100.00
chip_sw_sysrst_ctrl_reset				2	2	100.00
	chip_sw_pwrmgr_sysrst_ctrl_reset	696.990s	8087.401us	1	1	100.00
	chip_sw_sysrst_ctrl_reset	967.620s	24708.633us	1	1	100.00
chip_sw_sysrst_ctrl_inputs				1	1	100.00
	chip_sw_sysrst_ctrl_inputs	152.140s	3101.265us	1	1	100.00
chip_sw_sysrst_ctrl_outputs				1	1	100.00
	chip_sw_sysrst_ctrl_outputs	193.720s	3703.350us	1	1	100.00
chip_sw_sysrst_ctrl_in_irq				1	1	100.00
	chip_sw_sysrst_ctrl_in_irq	323.950s	4620.718us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_wakeup				1	1	100.00
	chip_sw_sysrst_ctrl_reset	967.620s	24708.633us	1	1	100.00
chip_sw_sysrst_ctrl_sleep_reset				1	1	100.00
	chip_sw_sysrst_ctrl_reset	967.620s	24708.633us	1	1	100.00
chip_sw_sysrst_ctrl_ec_rst_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2116.000s	21049.703us	1	1	100.00
chip_sw_sysrst_ctrl_flash_wp_l				1	1	100.00
	chip_sw_sysrst_ctrl_ec_rst_l	2116.000s	21049.703us	1	1	100.00
chip_sw_sysrst_ctrl_ulp_z3_wakeup				1	2	50.00
	chip_sw_sysrst_ctrl_ulp_z3_wakeup	349.760s	6713.759us	1	1	100.00
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3236.010s	34555.619us	0	1	0.00
chip_sw_usbdev_vbus				1	1	100.00
	chip_sw_usbdev_vbus	138.560s	3674.104us	1	1	100.00
chip_sw_usbdev_pullup				1	1	100.00
	chip_sw_usbdev_pullup	156.190s	2526.242us	1	1	100.00
chip_sw_usbdev_aon_pullup				1	1	100.00
	chip_sw_usbdev_aon_pullup	229.800s	3421.241us	1	1	100.00
chip_sw_usbdev_setup_rx				1	1	100.00
	chip_sw_usbdev_setuprx	283.730s	3368.830us	1	1	100.00
chip_sw_usbdev_config_host				1	1	100.00
	chip_sw_usbdev_config_host	846.030s	7825.545us	1	1	100.00
chip_sw_usbdev_pincfg				1	1	100.00
	chip_sw_usbdev_pincfg	5359.680s	31917.987us	1	1	100.00
chip_sw_usbdev_tx_rx				1	1	100.00
	chip_sw_usbdev_dpi	1808.800s	11611.923us	1	1	100.00
chip_sw_usbdev_toggle_restore				1	1	100.00
	chip_sw_usbdev_toggle_restore	173.290s	3143.673us	1	1	100.00

V2S

1/2 passed

50.00 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_aes_masking_off				1	1	100.00
	chip_sw_aes_masking_off	154.260s	2491.445us	1	1	100.00
chip_sw_rv_core_ibex_lockstep_glitch				0	1	0.00
	chip_sw_rv_core_ibex_lockstep_glitch	79.910s	2396.252us	0	1	0.00

17/26 passed

65.38 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
chip_sw_coremark				1	1	100.00
	chip_sw_coremark	9395.300s	68507.880us	1	1	100.00
chip_sw_power_max_load				1	1	100.00
	chip_sw_power_virus	1058.400s	6116.679us	1	1	100.00
rom_e2e_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	184.280s	3840.168us	0	1	0.00
	rom_e2e_jtag_debug_dev	194.330s	3579.824us	0	1	0.00
	rom_e2e_jtag_debug_rma	390.590s	6985.973us	0	1	0.00
rom_e2e_jtag_inject				0	3	0.00
	rom_e2e_jtag_inject_test_unlocked0	71.360s	2646.137us	0	1	0.00
	rom_e2e_jtag_inject_dev	58.120s	2177.064us	0	1	0.00
	rom_e2e_jtag_inject_rma	81.240s	2857.724us	0	1	0.00
rom_e2e_self_hash				0	1	0.00
	rom_e2e_self_hash	42.604s	0.000us	0	1	0.00
chip_sw_clkmgr_jitter_cycle_measurements				0	1	0.00
	chip_sw_clkmgr_jitter_frequency	283.920s	3918.223us	0	1	0.00
chip_sw_edn_boot_mode				1	1	100.00
	chip_sw_edn_boot_mode	303.650s	2752.196us	1	1	100.00
chip_sw_edn_auto_mode				1	1	100.00
	chip_sw_edn_auto_mode	508.010s	3768.402us	1	1	100.00
chip_sw_edn_sw_mode				1	1	100.00
	chip_sw_edn_sw_mode	1141.910s	8714.845us	1	1	100.00
chip_sw_edn_kat				1	1	100.00
	chip_sw_edn_kat	203.790s	2859.821us	1	1	100.00
chip_sw_flash_memory_protection				1	1	100.00
	chip_sw_flash_ctrl_mem_protection	656.190s	4926.200us	1	1	100.00
chip_sw_otp_ctrl_vendor_test_csr_access				1	1	100.00
	chip_sw_otp_ctrl_vendor_test_csr_access	67.040s	2439.228us	1	1	100.00
chip_sw_otp_ctrl_escalation				0	1	0.00
	chip_sw_otp_ctrl_escalation	177.250s	2798.891us	0	1	0.00
chip_sw_sensor_ctrl_deep_sleep_wake_up				1	1	100.00
	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	276.490s	5579.318us	1	1	100.00
chip_sw_pwrmgr_usb_clk_disabled_when_active				1	1	100.00
	chip_sw_pwrmgr_usb_clk_disabled_when_active	331.980s	5201.749us	1	1	100.00
chip_sw_all_resets				1	1	100.00
	chip_sw_pwrmgr_all_reset_reqs	815.630s	9445.377us	1	1	100.00
chip_rv_dm_perform_debug				0	3	0.00
	rom_e2e_jtag_debug_test_unlocked0	184.280s	3840.168us	0	1	0.00
	rom_e2e_jtag_debug_dev	194.330s	3579.824us	0	1	0.00
	rom_e2e_jtag_debug_rma	390.590s	6985.973us	0	1	0.00
chip_sw_rv_dm_access_after_hw_reset				1	1	100.00
	chip_sw_rv_dm_access_after_escalation_reset	345.820s	5683.711us	1	1	100.00
chip_sw_plic_alerts				1	1	100.00
	chip_sw_all_escalation_resets	440.410s	5213.904us	1	1	100.00
tick_configuration				1	1	100.00
	chip_sw_rv_timer_systick_test	5335.440s	37616.274us	1	1	100.00
counter_wrap				1	1	100.00
	chip_sw_rv_timer_systick_test	5335.440s	37616.274us	1	1	100.00
chip_sw_spi_device_output_when_disabled_or_sleeping				1	1	100.00
	chip_sw_spi_device_pinmux_sleep_retention	188.370s	3619.761us	1	1	100.00
chip_sw_uart_watermarks				1	1	100.00
	chip_sw_uart_tx_rx	327.210s	4456.797us	1	1	100.00
chip_sw_usbdev_stream				1	1	100.00
	chip_sw_usbdev_stream	3120.650s	19139.749us	1	1	100.00

unmapped

7/11 passed

63.64 %

Testpoint	Test	Max Runtime	Sim Time	Pass	Total	%
Unmapped				7	11	63.64
	chip_sival_flash_info_access	235.650s	3950.552us	1	1	100.00
	chip_sw_rstmgr_rst_cnsty_escalation	18.800s	10.400us	0	1	0.00
	chip_sw_otp_ctrl_rot_auth_config	4.810s	0.000us	0	1	0.00
	chip_sw_otp_ctrl_ecc_error_vendor_test	170.020s	2872.740us	1	1	100.00
	chip_sw_otp_ctrl_descrambling	139.550s	2617.552us	1	1	100.00
	chip_sw_pwrmgr_lowpower_cancel	186.900s	3359.961us	1	1	100.00
	chip_sw_pwrmgr_sleep_wake_5_bug	8.234s	0.000us	0	1	0.00
	chip_sw_flash_ctrl_write_clear	172.590s	2865.111us	1	1	100.00
	ate_bootstrap_flash_erase	569.410s	10010.140us	0	1	0.00
	ate_bootstrap_one_frame	6327.530s	43165.045us	1	1	100.00
	ate_bootstrap_disjoint	9012.740s	78856.689us	1	1	100.00

Error Messages

	Test	seed	line	log context
Some pass patterns missing: ['^TEST PASSED (UVM_)?CHECKS$']				24 test runs
	chip_sw_pwrmgr_sleep_wake_5_bug	53736913386387812016065885358763470492709406625406834924902303588030878182046	None	---- STDERR ---- Another command (pid=2068951) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	26475766640051032472922289672593859758574112087818808275971665976783217410685	None	Another command (pid=569953) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=463886) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=572254) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_dev	95945823750816177337179760266999373632070507594081953587436491373221258663696	None	Another command (pid=581099) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=451620) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=563137) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod	111918304047501492668051339868847423993523837876128283711782800306213098078211	None	Another command (pid=613255) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=582073) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=616739) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_prod_end	114794207274253832326475852169148876902961005548157231845756173773577596420761	None	---- STDERR ---- Another command (pid=581099) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_good_rma	96520685968737369374281573728172285630704155769530522171154584097263430306600	None	Another command (pid=581099) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=592742) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=451620) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	4589115842766891255951574564643255159348191268998085969053019289164151976405	None	Another command (pid=598993) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=579977) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=611813) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_dev	109856512501859866934759801023076030701219855085750437421984788088053610314277	None	---- STDERR ---- Another command (pid=467540) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod	96964457040777965619771013193086307809007060785898228531012681299331610631236	None	Another command (pid=665547) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=689322) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=686331) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	58299006194715145959024057244643945860174247915741301952086609176561483692382	None	Another command (pid=598993) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=579977) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=611813) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_good_b_bad_rma	93492910076221298378326744398019606667873336234689407468577648654180655155703	None	---- STDERR ---- Another command (pid=463886) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=570322) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	72252024793237635768203025269965618023355036374217601044932463228007489672004	None	Another command (pid=384195) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=466342) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=435604) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_dev	49545552937122814287370661110481779336811274924780396959232292372208796105440	None	Another command (pid=451620) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=563137) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=535917) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod	17527111787352236178582910958764582900958046568999713481526990816229719231839	None	---- STDERR ---- Another command (pid=559444) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	114224288123557305187085671300601698233242863969057235664045185720677119462817	None	Another command (pid=597647) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=425158) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=579278) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_boot_policy_valid_a_bad_b_good_rma	98262019514197835290372804564766536120443776465076512779516232931531906512619	None	Another command (pid=570322) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=381267) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=568805) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_b_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_test_unlocked0	69440247427999222989020528243216116582767505293890163444147853099092487275176	None	Another command (pid=378130) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=432289) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=450585) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_dev	71348700959853851269315383141839246805584241524174270419426682552289179978778	None	---- STDERR ---- Another command (pid=378130) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod	16626053029704623746787495309931625524238897217086566466789079902077261435535	None	Another command (pid=592742) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=451620) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=592801) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_prod_end	70835609900958996204392679151348072438372593276121741537242831757791107845702	None	Another command (pid=465868) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=567664) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=447275) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_asm_init_rma	1139669889175501994884761605120172461761046013511623860103772455615822244888	None	Another command (pid=595160) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=598993) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=579977) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_prod_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_volatile_raw_unlock	106487258410272869986257508716620024514691770328570673606132372933764467839508	None	Another command (pid=466342) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=435604) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=467540) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_raw_unlock	32318160025830872482060956649823129557499061291980711798676446233995164459232	None	Another command (pid=443019) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=448205) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=378130) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e:empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv': target 'empty_test_slot_a_fake_ecdsa_test_key_0_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
	rom_e2e_self_hash	79443485230572334905322082259825743980066355161041776203233389130460648922069	None	Another command (pid=448205) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=378130) is running. Waiting for it to complete on the server (server_pid=289279)... Another command (pid=419787) is running. Waiting for it to complete on the server (server_pid=289279)... WARNING: Target pattern parsing failed. ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD ERROR: Build did NOT complete successfully _run_cmd -> had a non-zero return code of 1. make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:58: sw_build] Error 1
Error-[NOA] Null object access				7 test runs
	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	52350683372755399959770376982925207154354326486365188064807146086280207165734	332	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_test_unlocked0	55790610794737223347572025482101536055530302875626617051930219977472789466522	324	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_dev	70246050795646436583902188783471916016659675689907940582444134485575561517064	324	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_debug_rma	63248319657129581851227074114769870503971087335292246130933087212564341952502	357	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 903 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_test_unlocked0	111657469339965404460344019009377919976093711068983077574291451520392159062001	308	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1108 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_dev	67357375763837946852419183193464747261508696167090463091738346105333844934200	310	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
	rom_e2e_jtag_inject_rma	25211804469056665602818146741209377219799425238535402650847560845203045023896	312	src/lowrisc_dv_jtag_dmi_agent_0/jtag_rv_debugger.sv, 1078 The object at dereference depth 1 is being used before it was constructed/allocated. Please make sure that the object is allocated before using it.
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				6 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_prod	88275888513298373418182937611275324168109945607858083877957164950721487705911	373	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_prod_end	9232555164262589315798482070970405764429685781216394925860490905786708211420	372	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_bad_rma	99775440356065784947620036726453241286167729217008667518181742815331677005163	372	UVM_INFO @ 10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod	114817751196431184837146446442018086836638247641796069281605340440113437475320	333	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	102348203646947247501138357768744138692937270889124253871780834536952894467275	333	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_rma	4991789295082479435341758016472720729451509430519223690179469949019816651676	333	UVM_INFO @ 10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_base_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				3 test runs
	chip_sw_kmac_entropy	21332205934189722890137517392865446053466730920280066440301115389473495337791	331	UVM_INFO @ 12018.563901 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_hmac_multistream	108294815383217120960928931014351455943363299994183477583038927087552961892539	375	UVM_INFO @ 12026.861496 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_keymgr_sideload_otbn	49515414679061904226034919434184655096824822109172422469438186118394577062228	341	UVM_INFO @ 20026.629735 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [lc_walkthrough_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				3 test runs
	chip_sw_lc_walkthrough_dev	90516373818522583949844834605938109726893086596725602946697585614305528078745	369	UVM_INFO @ 11147.378632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_prod	97831183659231553769859859393960801399951044450760321926321895452953451897907	369	UVM_INFO @ 10112.628672 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_lc_walkthrough_rma	48255159874916623541146356665179863523838313978480155386712940122548154260296	346	UVM_INFO @ 5996.596926 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(rstreqs[*] && (reset_cause == HwReq))'				3 test runs
	chip_sw_pwrmgr_random_sleep_all_reset_reqs	60023238765963355538456632968679501658825096297806424730664576474582916004982	349	UVM_ERROR @ 13343.581000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 13343.581000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	518881470738171150645673930476695962825184460614856168877642494064436648187	319	UVM_ERROR @ 5983.416000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 5983.416000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_deep_sleep_por_reset	55767417898701030849328014406131161898129434599191613888806481246606734607869	330	UVM_ERROR @ 7948.047500 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A UVM_INFO @ 7948.047500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_.signed..scr.vmem could not be opened for r mode				3 test runs
	rom_e2e_sigverify_always_a_nothing_b_bad_prod	66405786404995174697185003391340617239691895888514901503149887923932263149224	327	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	40471773757744123156643741408412520668179024743421339675983113560495536611316	333	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_nothing_b_bad_rma	109404936500304815984659254725597158859746731663896666667666901133889066573907	333	UVM_INFO @ 10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell((pwrmgr_data_o.done == MuBi4True)))'				2 test runs
	chip_sw_pwrmgr_sleep_power_glitch_reset	19970179245494808318056745248058116483072339971804974160506993948081496024858	318	UVM_ERROR @ 2530.756382 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 2530.756382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	chip_sw_pwrmgr_random_sleep_power_glitch_reset	28960579574454927501317536926038019849325066525115901093281952252862564584445	371	UVM_ERROR @ 15643.697272 us: (rom_ctrl.sv:586) [ASSERT FAILED] PwrmgrDataChk_A UVM_INFO @ 15643.697272 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	107468458543757965507505979453371937961927239989771995689513484020999151145686	367	UVM_INFO @ 10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	78779534571898753373964035275617434332970216607096330421186489864596950313649	330	UVM_INFO @ 10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				2 test runs
	rom_e2e_sigverify_always_a_bad_b_bad_dev	33784885239128542363044367017642070963199039188024321850896632528700058390579	373	UVM_INFO @ 10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
	rom_e2e_sigverify_always_a_bad_b_nothing_dev	95008761201306463942822944998271435793275975221572344780818226805013778319665	333	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (sec_cm_pkg.sv:48) [sec_cm_pkg::find_sec_cm_if_proxy] no proxy with path rstmgr_aon.u_d0_spi_host.leaf_rst_path				1 test run
	chip_sw_rstmgr_rst_cnsty_escalation	114505224984405857966659006602482807577063181248245731872947740052513187807458	306	UVM_INFO @ 10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_sleep_pin_mio_dio_val_vseq.sv:92) [chip_sw_sleep_pin_mio_dio_val_vseq] Check failed cfg.chip_vif.mios_if.pins[i] === exp (* [] vs xz [z]) for MIO[*]				1 test run
	chip_sw_sleep_pin_mio_dio_val	14442235115976653162041269757492314520503680203397843680910445438524033850855	456	UVM_INFO @ 3551.898000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty				1 test run
	chip_sw_spi_device_pass_through_collision	2761541003101793548938441362188763778704301263412334630493179193690111615364	332	UVM_INFO @ 3319.154324 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [flash_ctrl_lc_rw_en_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_flash_ctrl_lc_rw_en	42410144680763088104320267111789452622807816520209541410080221960935012491147	314	UVM_INFO @ 3433.308823 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to *				1 test run
	chip_sw_otp_ctrl_lc_signals_rma	109558646220590117592050467497702787706358947248353102221131973373492123791129	347	UVM_INFO @ 7515.216653 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'				1 test run
	chip_sw_otp_ctrl_escalation	40492808229860733399905522305231933398189691690007359588859844215515051363150	316	UVM_ERROR @ 2798.890692 us: (lc_ctrl.sv:884) [ASSERT FAILED] LcInitDoneSticky_A UVM_INFO @ 2798.890692 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[Otp]] file otp_img_test_unlocked0_manuf_empty.*.vmem could not be opened for r mode				1 test run
	chip_sw_otp_ctrl_rot_auth_config	25488891017581837106950426701835465045351031956650256346289952265765347322626	287	UVM_INFO @ 0.000000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_base_vseq.sv:864) virtual_sequencer [chip_sw_lc_walkthrough_vseq] max attempt reached to get lc status LcExtClockSwitched!				1 test run
	chip_sw_lc_walkthrough_prodend	108095617854685727435702822622777943622297666104389776739499577584153274729549	313	UVM_INFO @ 26565.030388 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '((~rst_ni) === (~seed_en_q))'				1 test run
	chip_sw_pwrmgr_full_aon_reset	85706801677038719626207583340017452434299164856465436230533295789083404015895	308	UVM_ERROR @ 2547.405180 us: (otbn_rnd.sv:233) [ASSERT FAILED] UrndNoReseedOnReset_A UVM_INFO @ 2547.405180 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:322) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns				1 test run
	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	45496038336620600241182816890186079485391298968049717743808612918196188601516	337	UVM_INFO @ 34555.618929 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:342)] CHECK-fail: Expect alert *!				1 test run
	chip_sw_alert_test	67787064389669211068939490972930225021605184064917118302719761740317729590021	307	UVM_INFO @ 2826.137784 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_alerts	97730390822304794098068543484004640248865356985466710130865534857139164287105	308	UVM_INFO @ 2991.939651 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Job timed out after * minutes				1 test run
	chip_sw_alert_handler_lpg_sleep_mode_pings	72387242240572331900767421668475903877205324232217379876646026029863151332729	None
UVM_ERROR @ * us: (sw_logger_if.sv:526) [clkmgr_jitter_frequency_test_sim_dv(sw/device/lib/testing/test_framework/ottf_alerts.c:172)] ERROR: Alert * is asserted but not expected				1 test run
	chip_sw_clkmgr_jitter_frequency	93411338557986650612886425138522034550740880129377255296333754747921426675939	348	UVM_INFO @ 3918.222993 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_dm_access_after_wakeup_vseq.sv:93) [chip_sw_rv_dm_access_after_wakeup_vseq] Timed out waiting for device to wakeup from deep sleep.				1 test run
	chip_sw_rv_dm_access_after_wakeup	1103539166974286327293616014622118814007756201051329777756042920086293844050	334	UVM_INFO @ 12876.390982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_rv_core_ibex_lockstep_glitch_vseq.sv:738) [chip_sw_rv_core_ibex_lockstep_glitch_vseq] Check failed alert_major_internal == exp_alert_major_internal (* [] vs [*]) Major alert did not match expectation.				1 test run
	chip_sw_rv_core_ibex_lockstep_glitch	32207263331355797879428476704646376524578415385939205827359950998266759634342	329	UVM_INFO @ 2396.252338 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_idle_load_vseq.sv:24) [chip_sw_power_idle_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_idle_load	108148284793263060998538345773741954900644235114333607460936628755523894605455	323	UVM_INFO @ 15354.058508 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (chip_sw_power_sleep_load_vseq.sv:47) [chip_sw_power_sleep_load_vseq] timeout waiting for SW sync GPIO (*)				1 test run
	chip_sw_power_sleep_load	29639276384470530179386609000898486551170749906401041493962909482843072903476	342	UVM_INFO @ 15060.571982 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/lib/testing/autogen/isr_testutils.c:41)] CHECK-fail: Only adc_ctrl IRQ * expected to fire. Actual IRQ state = *				1 test run
	chip_sw_ast_clk_rst_inputs	75342083796406871143267015510996626386225353374069073120853429672906406780912	332	UVM_INFO @ 10669.943320 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (csr_utils_pkg.sv:614) [csr_utils_pkg::csr_spinwait.isolation_fork] timeout chip_reg_block.spi_device.cmd_info_.opcode (addr=, Comparison=CompareOpEq, exp_data=*, call_count=1)				1 test run
	ate_bootstrap_flash_erase	77201101300286364774876333085325466341018362363501076881665758889727544135702	272	UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_exception_c_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_exception_c	38439737266783583859685474998747164730052490335170224304422829874337896443351	324	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 4954.602041 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (chip_sw_rom_e2e_base_vseq.sv:37) [chip_sw_rom_e2e_shutdown_output_vseq] Check failed "OpenTitan:--*				1 test run
	rom_e2e_shutdown_output	21564672374931468791068404993944073211907926495899060884230193352240742533429	317	" == "OpenTitan:4001-0002-01 " UVM_INFO @ 8240.378013 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	97013459219996136579311454685874821556832775552931267521480121040857907006668	330	UVM_INFO @ 10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_FATAL @ * us: (mem_bkdr_util.sv:658) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_.signed..scr.vmem could not be opened for r mode				1 test run
	rom_e2e_sigverify_always_a_nothing_b_bad_dev	104164589608476980447109980214261087694887328792529372288325926338621604855926	332	UVM_INFO @ 10.260001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_keymgr_init_otp_invalid_meas_sim_dv(sw/device/silicon_creator/rom/e2e/keymgr/rom_e2e_keymgr_init_test.c:38)] DIF-fail: dif_otp_ctrl_get_digest( &otp_ctrl, kDifOtpCtrlPartitionCreatorSwCfg, &creator_digest) returns *				1 test run
	rom_e2e_keymgr_init_rom_ext_invalid_meas	82944206323865246150519769854756011651325303177128500534945958949965639612704	324	UVM_INFO @ 15769.486258 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
Offending '$stable(key_data_i)'				1 test run
	rom_keymgr_functest	24552052756447135341611419896713351237684461853970899290041081000612348797398	332	UVM_ERROR @ 4847.143962 us: (kmac_core.sv:464) [ASSERT FAILED] KeyDataStableWhenValid_M UVM_INFO @ 4847.143962 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---
UVM_ERROR @ * us: (cip_base_scoreboard.sv:575) scoreboard [scoreboard] On interface chip_reg_block, item had unexpected d_error value(predicted , but saw ).				1 test run
	chip_csr_mem_rw_with_rand_reset	113683693786469251487942465395302332501276253037468114280657713145725177547520	224	TL item was: req: (cip_tl_seq_item@30784) { a_addr: 'h10434 a_data: 'heef372c5 a_mask: 'hf a_size: 'h2 a_param: 'h0 a_source: 'h4 a_opcode: 'h4 a_user: 'h1a526 d_param: 'h0 d_source: 'h4 d_data: 'h0 d_size: 'h2 d_opcode: 'h1 d_error: 'h0 d_sink: 'h0 d_user: 'hd2a a_valid_delay: 'h0 d_valid_delay: 'h0 a_valid_len: 'h0 d_valid_len: 'h0 req_abort_after_a_valid_len: 'h0 rsp_abort_after_d_valid_len: 'h0 req_completed: 'h0 rsp_completed: 'h0 tl_intg_err_type: TlIntgErrNone max_ecc_errors: 'h3 } Reasons for predicted error: '{"Fetch from CSR"} . UVM_INFO @ 2139.260700 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER] --- UVM Report catcher Summary ---